Tuning L2 cache on or off has no effect? (Athlon "Thunderbird" 1200C on Asus A7V133-C) \ VOGONS

Tuning L2 cache on or off has no effect? (Athlon "Thunderbird" 1200C on Asus A7V133-C)

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First post, by dormcat

Posted on 2021-08-30, 10:54

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Hi all,

I got a system with Athlon "Thunderbird" 1200C on Asus A7V133-C last week and, after some painstaking troubleshooting (turned out the SDRAM was faulty), I started testing the system with CPU-Z Vintage Edition and TOPBENCH. The BIOS has the option of turning L1 and L2 caches on and off; turning off L1 cache would drop the speed significantly to be equivalent to 486SX-25

However, unlike my Pentium-MMX build, turning L2 cache on or off on this T-bird build has no effect, with the difference of benchmark scores less than 1%, either with or without L1 cache.

Could it be
1. Norma: turning L2 off has little effect on T-bird builds
2. Normal: turning L2 off does slow down the system but CPU-Z and TOPBENCH simply can't reflect this; try another benchmark software
3. Abnormal: there's something wrong with CPU and/or MB

I know that companies like PCChips had the illegitimate practice of making fake L2 chips on their 486-era MB but I don't think Asus would do so in the era of P3/T-bird.

Reply 1 of 5, by Falcosoft

Posted on 2021-08-30, 13:07

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dormcat wrote on 2021-08-30, 10:54:
Hi all, […]
Show full quote

Hi all,

I got a system with Athlon "Thunderbird" 1200C on Asus A7V133-C last week and, after some painstaking troubleshooting (turned out the SDRAM was faulty), I started testing the system with CPU-Z Vintage Edition and TOPBENCH. The BIOS has the option of turning L1 and L2 caches on and off; turning off L1 cache would drop the speed significantly to be equivalent to 486SX-25

CPUZvintage_wL1.jpgCPUZvintage_woL1.jpg
topbench_wL1.jpgtopbench_woL1.jpg

However, unlike my Pentium-MMX build, turning L2 cache on or off on this T-bird build has no effect, with the difference of benchmark scores less than 1%, either with or without L1 cache.

Could it be
1. Norma: turning L2 off has little effect on T-bird builds
2. Normal: turning L2 off does slow down the system but CPU-Z and TOPBENCH simply can't reflect this; try another benchmark software
3. Abnormal: there's something wrong with CPU and/or MB

I know that companies like PCChips had the illegitimate practice of making fake L2 chips on their 486-era MB but I don't think Asus would do so in the era of P3/T-bird.

You can check if the problem is 2 or 3 by using synthetic memory benchmarks that use different data block sizes.
The Tbird has rather big L1 cache (64K+64K) and not so big L2 cache (256K). So you should look at the results at 128K and 256K. If L2 cache is enabled then 128K-256K results should be slower than the L1 results (up to 64K) and faster than main memory results (bigger than 256K). If L2 cache is disabled then 128K and 256K results should be roughly the same as main memory results.
You can use e.g. cachemem under DOS or Sisoft Sandra under Windows to test this.

Filename: cachemem.zip
File size: 39.44 KiB
Downloads: 30 downloads
File license: Public domain

1666Mhz Athlon Tbred cachemem results with enabled 256K L2 cache:

1Cache size/Memory speed info tool 2.65MMX - (c) 1999-2001, LRMS - DJGPP compiled
2CPUID support detected... 'AuthenticAMD' with FPU TSC MMX
3Family=6 Model=8 Step=1 Type=0 Chipset (Vendor/Device ID(Rev)): VIA/0305(03)
4CPU clock: 1666.7 MHz
5Using 32MB physical memory block (alignment = 32)
6Bandwidth - MMX linear access test... Read/Write/Copy (MB/s)
7Block of     1KB: 14530.9 / 12714.2 / 17031.7
8Block of     2KB: 13734.0 / 12100.2 / 17747.5
9Block of     4KB: 14121.4 / 12077.9 / 18113.1
10Block of     8KB: 14323.3 / 12022.0 / 18300.7
11Block of    16KB: 14426.3 / 11994.4 / 18397.8
12Block of    32KB: 14482.7 / 11980.6 / 17776.0
13Block of    64KB: 14440.5 / 11880.6 / 4507.4
14Block of   128KB: 4958.2 / 5047.2 / 4493.7
15Block of   256KB: 4960.9 / 5050.8 / 489.8
16Block of   512KB: 877.2 / 327.7 / 490.0
17Block of  1024KB: 876.6 / 329.0 / 490.6
18Block of  2048KB: 873.2 / 355.3 / 490.5
19Block of  4096KB: 872.0 / 363.7 / 490.5
20Block of  8192KB: 871.4 / 367.4 / 490.5
21Block of 16384KB: 871.1 / 370.3 / 490.4
22Block of 32768KB: 871.0 / 367.6
23Latency - Memory walk tests... ("pointer chasing")
24Null size:    4 cycles   1 cycles (overhead 66 cycles)
25           steps:   4   8  16  32  64 128 256 512  1k  2k  4k (bytes)
26Block of     1KB:   4   4   4   4   4   4   4   4   -   -   - cycles
27Block of     2KB:   4   4   4   4   4   4   4   4   4   -   - cycles
28Block of     4KB:   4   4   4   4   4   4   4   4   4   4   - cycles
29Block of     8KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
30Block of    16KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
31Block of    32KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
32Block of    64KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
33Block of   128KB:   4   5   9  18  20  20  20  20  20  20  20 cycles
34Block of   256KB:   4   5   9  18  20  20  20  20  20  20  20 cycles
35Block of   512KB:  15  27  48  96 184 230 231 234 240 253 278 cycles
36Block of  1024KB:  15  27  48  96 184 229 231 234 240 253 279 cycles
37Block of  2048KB:  15  27  48  96 184 230 232 236 245 261 294 cycles
38Block of  4096KB:  15  27  48  96 184 230 232 237 246 263 299 cycles
39Block of  8192KB:  15  27  48  97 183 230 232 237 246 264 301 cycles
40Block of 16384KB:  15  27  48  96 184 230 232 237 247 265 303 cycles
41Block of 32768KB:  15  27  48  97 184 230 232 237 247 265 303 cycles
42This system appears to have 2 cache levels (enabled).
43L1 cache (64KB) speed (MB/s): Read=14482.7, Write=11980.6
44L2 cache (256KB) speed (MB/s): Read=4958.2, Write=5047.2
45Main memory speed (MB/s): Read=871.1, Write=370.3

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Reply 2 of 5, by Standard Def Steve

Posted on 2021-08-31, 00:05

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Joined: 2012-09-15, 08:04

It's probably not turning off the L2 at all, because you would notice a difference.

I've had at least one system in the past outright ignore the L2 cache toggle in the BIOS. It was all or nothing with that particular system (turning off L1 in the BIOS would disable L2 as well). With both caches disabled, you could actually see the XP welcome screen fade in, using around 12 different shades of blue. Normally, you don't even see that fade-in effect because it happens so quickly. Who knew XP had speed-sensitive visual effects?

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Reply 3 of 5, by dormcat

Posted on 2021-08-31, 05:54

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Falcosoft wrote on 2021-08-30, 13:07:

You can check if the problem is 2 or 3 by using synthetic memory benchmarks that use different data block sizes.
The Tbird has rather big L1 cache (64K+64K) and not so big L2 cache (256K). So you should look at the results at 128K and 256K. If L2 cache is enabled then 128K-256K results should be slower than the L1 results (up to 64K) and faster than main memory results (bigger than 256K). If L2 cache is disabled then 128K and 256K results should be roughly the same as main memory results.
You can use e.g. cachemem under DOS or Sisoft Sandra under Windows to test this.

Thanks a lot! Turned out the L2 could be disabled with L1 alone enabled, but L2 always got disabled when L1 was disabled, just like Standard Def Steve said:

Standard Def Steve wrote on 2021-08-31, 00:05:

I've had at least one system in the past outright ignore the L2 cache toggle in the BIOS. It was all or nothing with that particular system (turning off L1 in the BIOS would disable L2 as well).

I ran cachemem twice just to make sure I had either enabled or disabled L2 back and forth, with L1 disabled.

With L1 and L2 both enabled (I'll just list Latency tests):

1           steps:   4   8  16  32  64 128 256 512  1k  2k  4k (bytes)
2Block of     1KB:   4   4   4   4   4   4   4   4   -   -   - cycles
3Block of     2KB:   4   4   4   4   4   4   4   4   4   -   - cycles
4Block of     4KB:   4   4   4   4   4   4   4   4   4   4   - cycles
5Block of     8KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
6Block of    16KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
7Block of    32KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
8Block of    64KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
9Block of   128KB:   4   5   9  10  20  20  20  20  20  20  20 cycles
10Block of   256KB:   4   5   9  10  20  20  20  20  20  20  20 cycles
11Block of   512KB:  19  29  59 109 181 182 184 187 194 207 234 cycles
12Block of  1024KB:  19  29  59 108 181 182 184 187 194 208 234 cycles
13Block of  2048KB:  19  29  59 109 182 183 185 190 200 218 261 cycles
14Block of  4096KB:  19  29  59 109 182 183 186 191 201 223 264 cycles
15Block of  8192KB:  19  29  59 109 182 184 186 191 202 224 267 cycles
16Block of 16384KB:  19  29  59 109 182 183 186 192 203 225 269 cycles
17Block of 32768KB:  19  29  59 109 182 183 186 191 203 225 270 cycles
18This system appears to have 2 cache levels (enabled).
19L1 cache (64KB) speed (MB/s): Read=11301.1, Write=9191.6
20L2 cache (256KB) speed (MB/s): Read=3684.8, Write=3682.9
21Main memory speed (MB/s): Read=964.2, Write=288.5

With L1 enabled and L2 disabled:

1           steps:   4   8  16  32  64 128 256 512  1k  2k  4k (bytes)
2Block of     1KB:   4   4   4   4   4   4   4   4   -   -   - cycles
3Block of     2KB:   4   4   4   4   4   4   4   4   4   -   - cycles
4Block of     4KB:   4   4   4   4   4   4   4   4   4   4   - cycles
5Block of     8KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
6Block of    16KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
7Block of    32KB:   4   4   4   4   4   4   4   4   4   4   4 cycles
8Block of    64KB:   5   4   4   4   5   5   4   4   4   4   4 cycles
9Block of   128KB:  20  29  58 109 181 182 184 187 194 207 234 cycles
10Block of   256KB:  19  29  59 109 181 183 184 187 194 207 234 cycles
11Block of   512KB:  19  29  58 109 181 182 184 188 194 207 234 cycles
12Block of  1024KB:  19  29  59 109 181 183 184 187 194 207 234 cycles
13Block of  2048KB:  19  29  59 109 181 183 185 191 200 219 259 cycles
14Block of  4096KB:  19  29  59 109 182 183 186 191 202 222 263 cycles
15Block of  8192KB:  19  29  59 109 182 183 186 191 202 224 267 cycles
16Block of 16384KB:  19  29  59 109 182 183 186 192 203 225 269 cycles
17Block of 32768KB:  19  29  59 109 182 183 186 192 203 225 269 cycles
18This system appears to have 1 cache levels (enabled).
19L1 cache (64KB) speed (MB/s): Read=11300.9, Write=9191.5
20Main memory speed (MB/s): Read=964.3, Write=286.1

With "L1 disabled and L2 enabled" (as shown in BIOS), but L2 was in fact disabled altogether:

1           steps:   4   8  16  32  64 128 256 512  1k  2k  4k (bytes)
2Block of     1KB: 242 242 242 242 242 242 243 242   -   -   - cycles
3Block of     2KB: 242 242 242 242 242 242 242 243 242   -   - cycles
4Block of     4KB: 242 242 242 242 242 242 243 242 242 242   - cycles
5Block of     8KB: 242 242 242 242 242 243 242 242 242 242 242 cycles
6Block of    16KB: 242 242 243 242 242 242 242 242 242 242 243 cycles
7Block of    32KB: 242 242 243 242 242 243 245 248 255 268 296 cycles
8Block of    64KB: 242 242 242 242 244 243 245 248 255 268 295 cycles
9Block of   128KB: 242 242 242 242 242 243 245 248 255 268 295 cycles
10Block of   256KB: 242 242 242 242 242 243 245 248 255 268 295 cycles
11Block of   512KB: 242 242 242 242 242 243 245 248 255 270 295 cycles
12Block of  1024KB: 242 242 243 243 243 245 245 249 256 269 296 cycles
13Block of  2048KB: 242 242 243 244 245 246 249 251 259 272 299 cycles
14Block of  4096KB: 242 242 243 243 245 248 249 251 259 273 302 cycles
15Block of  8192KB: 242 243 242 243 245 247 249 252 260 273 301 cycles
16Block of 16384KB: 242 242 242 243 245 246 249 252 260 274 302 cycles
17Block of 32768KB: 242 243 242 244 245 247 249 252 260 274 302 cycles
18This system appears to have 0 cache levels (enabled).
19Main memory speed (MB/s): Read=37.6, Write=139.4

With L1 and L2 disabled:

1           steps:   4   8  16  32  64 128 256 512  1k  2k  4k (bytes)
2Block of     1KB: 242 242 242 242 242 242 243 242   -   -   - cycles
3Block of     2KB: 242 242 242 242 242 242 242 243 242   -   - cycles
4Block of     4KB: 242 242 242 242 242 242 242 243 242 242   - cycles
5Block of     8KB: 242 242 242 242 242 243 242 242 242 242 242 cycles
6Block of    16KB: 242 242 243 242 242 242 242 242 242 242 242 cycles
7Block of    32KB: 242 242 243 242 242 243 245 248 255 268 296 cycles
8Block of    64KB: 242 242 242 242 242 245 245 248 255 268 295 cycles
9Block of   128KB: 242 242 242 242 244 243 245 248 255 268 295 cycles
10Block of   256KB: 242 242 242 242 242 245 245 248 255 268 295 cycles
11Block of   512KB: 242 242 242 243 242 243 245 248 255 270 295 cycles
12Block of  1024KB: 242 243 242 243 243 245 245 249 256 269 296 cycles
13Block of  2048KB: 242 242 243 243 244 246 248 251 258 272 300 cycles
14Block of  4096KB: 242 242 242 243 245 246 249 251 259 273 300 cycles
15Block of  8192KB: 242 242 242 243 245 247 249 252 260 273 301 cycles
16Block of 16384KB: 244 242 243 243 245 247 249 252 260 274 302 cycles
17Block of 32768KB: 242 242 242 243 245 247 249 252 260 275 302 cycles
18This system appears to have 0 cache levels (enabled).
19Main memory speed (MB/s): Read=37.6, Write=139.4

With L1 enabled and L2 disabled, the difference could only be visible when data block sizes fell within 128KB or 256KB.

For the record, the Pentium-MMX 233MHz build (16KB L1 on CPU, 512KB L2 on MB) has a very different pattern:
Both enabled:

1           steps:   4   8  16  32  64 128 256 512  1k  2k  4k (bytes)
2Block of     1KB:   2   2   2   2   2   2   2   2   -   -   - cycles
3Block of     2KB:   2   2   2   2   2   2   2   2   2   -   - cycles
4Block of     4KB:   2   2   2   2   2   2   2   2   2   2   - cycles
5Block of     8KB:   2   2   2   2   2   2   2   2   2   2   2 cycles
6Block of    16KB:   2   2   2   2   2   2   2   2   2   2   2 cycles
7Block of    32KB:   4   7  12  17  17  17  17  17  17  17  17 cycles
8Block of    64KB:   4   7  12  17  17  17  17  18  17  17  17 cycles
9Block of   128KB:   4   7  12  17  17  17  17  17  17  17  17 cycles
10Block of   256KB:   4   7  12  17  17  17  17  17  17  17  17 cycles
11Block of   512KB:   4   7  12  17  17  17  17  17  17  17  17 cycles
12Block of  1024KB:   6  10  19  32  32  34  34  37  42  53  53 cycles
13Block of  2048KB:   6  10  19  32  32  33  34  37  42  53  53 cycles
14Block of  4096KB:   6  10  19  33  32  33  34  37  42  52  52 cycles
15Block of  8192KB:   6  10  19  32  32  33  34  37  42  52  53 cycles
16Block of 16384KB:   6  10  19  32  32  33  34  37  42  53  53 cycles
17This system appears to have 1 cache levels (enabled).
18L1 cache (16KB) speed (MB/s): Read=1289.4, Write=169.9
19Main memory speed (MB/s): Read=160.0, Write=169.2

L1 only:

1           steps:   4   8  16  32  64 128 256 512  1k  2k  4k (bytes)
2Block of     1KB:   2   2   2   2   2   2   2   2   -   -   - cycles
3Block of     2KB:   2   2   2   2   2   2   2   2   2   -   - cycles
4Block of     4KB:   2   2   2   2   2   2   2   2   2   2   - cycles
5Block of     8KB:   2   2   2   2   2   2   2   2   2   2   2 cycles
6Block of    16KB:   2   2   2   3   3   2   2   2   2   2   2 cycles
7Block of    32KB:   6  10  19  32  32  33  34  37  42  52  53 cycles
8Block of    64KB:   6  10  19  32  32  33  34  37  42  53  53 cycles
9Block of   128KB:   6  10  19  32  32  33  34  37  42  53  53 cycles
10Block of   256KB:   6  10  19  32  32  33  34  37  42  53  52 cycles
11Block of   512KB:   6  10  19  32  32  33  34  37  42  53  53 cycles
12Block of  1024KB:   6  10  19  32  32  33  34  37  42  53  53 cycles
13Block of  2048KB:   6  10  19  32  32  33  34  37  43  53  53 cycles
14Block of  4096KB:   6  10  19  32  32  33  34  37  42  52  53 cycles
15Block of  8192KB:   6  10  19  32  32  33  34  37  42  53  53 cycles
16Block of 16384KB:   6  10  19  32  32  33  34  37  42  53  52 cycles
17This system appears to have 1 cache levels (enabled).
18L1 cache (16KB) speed (MB/s): Read=1289.4, Write=169.9
19Main memory speed (MB/s): Read=160.0, Write=169.2

L2 only:

1           steps:   4   8  16  32  64 128 256 512  1k  2k  4k (bytes)
2Block of     1KB:  22  22  22  22  22  22  22  22   -   -   - cycles
3Block of     2KB:  22  22  22  22  22  22  22  22  22   -   - cycles
4Block of     4KB:  22  22  22  22  22  22  22  22  22  22   - cycles
5Block of     8KB:  22  22  22  22  23  23  24  22  22  22  22 cycles
6Block of    16KB:  22  22  22  22  22  22  23  22  22  22  22 cycles
7Block of    32KB:  22  22  22  22  22  22  22  22  22  22  22 cycles
8Block of    64KB:  22  22  22  22  22  22  22  22  22  22  22 cycles
9Block of   128KB:  22  22  22  22  22  22  22  22  22  22  22 cycles
10Block of   256KB:  22  22  22  22  22  22  22  22  22  22  22 cycles
11Block of   512KB:  22  22  22  22  22  22  22  22  22  22  22 cycles
12Block of  1024KB:  25  29  37  49  49  49  49  52  57  66  66 cycles
13Block of  2048KB:  25  29  37  49  49  49  49  52  57  66  66 cycles
14Block of  4096KB:  25  29  37  49  49  49  49  52  57  66  66 cycles
15Block of  8192KB:  25  29  37  49  49  49  49  52  57  66  66 cycles
16Block of 16384KB:  25  29  37  49  49  49  49  52  57  66  66 cycles
17This system appears to have 1 cache levels (enabled).
18L1 cache (512KB) speed (MB/s): Read=78.3, Write=92.7
19Main memory speed (MB/s): Read=51.3, Write=92.7

Both disabled:

1           steps:   4   8  16  32  64 128 256 512  1k  2k  4k (bytes)
2Block of     1KB:  58  58  58  58  58  58  58  58   -   -   - cycles
3Block of     2KB:  58  58  58  58  58  58  58  58  58   -   - cycles
4Block of     4KB:  58  58  58  58  58  59  60  60  64  69   - cycles
5Block of     8KB:  58  58  60  58  58  59  60  60  64  69  69 cycles
6Block of    16KB:  58  58  58  58  58  59  60  60  64  71  69 cycles
7Block of    32KB:  58  58  58  58  58  59  60  60  64  69  69 cycles
8Block of    64KB:  58  58  58  58  58  59  60  60  64  69  71 cycles
9Block of   128KB:  58  58  58  58  58  59  60  60  64  69  69 cycles
10Block of   256KB:  58  58  58  58  58  59  60  60  64  69  69 cycles
11Block of   512KB:  58  58  58  58  58  59  60  60  64  69  69 cycles
12Block of  1024KB:  58  58  58  58  58  59  60  60  64  69  69 cycles
13Block of  2048KB:  58  58  58  58  58  61  60  60  64  69  69 cycles
14Block of  4096KB:  58  58  58  58  58  59  62  60  64  69  69 cycles
15Block of  8192KB:  61  58  58  58  58  59  60  60  64  69  69 cycles
16Block of 16384KB:  58  58  58  58  58  59  60  60  64  71  69 cycles
17This system appears to have 0 cache levels (enabled).
18Main memory speed (MB/s): Read=27.2, Write=52.0

Hmm, seemed that cachemem couldn't recognize the 512KB external Pipelined Burst SRAM cache on Asus TXP4 MB.

Sorry for the long text; thanks again!

Reply 4 of 5, by Falcosoft

Posted on 2021-08-31, 07:19

Falcosoft Offline

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With L1 enabled and L2 disabled, the difference could only be visible when data block sizes fell within 128KB or 256KB.

Just as I said so. Compared to contemporary P4 the L2 cache was not so important to Athlon CPU's performance. That's why even the Duron with its anemic 64K L2 cache was more than competitive with P4 Celerons. That 64K+64K L1 cache is huge even compared to today's processor standards.
The biggest difference compared to your P1 MMX setup is that the Athlon Tbird has on-die L2 cache so the motherboard has nothing to do with it. Also that's why disabling L1 cache also disabled the whole cache hierarchy.
Cachemem has no specific cache level detection. It only infers the levels based on the measured bandwidth. You have not posted the bandwidth results but I assume that the relative difference between L2 bandwidth and main memory bandwidth was so small on your P1 MMX system that cachemem must have thought it is within margin of error.

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Reply 5 of 5, by dormcat

Posted on 2021-08-31, 07:59

dormcat Offline

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Falcosoft wrote on 2021-08-31, 07:19:

Cachemem has no specific cache level detection. It only infers the levels based on the measured bandwidth. You have not posted the bandwidth results but I assume that the relative difference between L2 bandwidth and main memory bandwidth was so small on your P1 MMX system that cachemem must have thought it is within margin of error.

Indeed, the difference was visible (-33% read bandwidth) yet much less than other read bandwidth differences (3-4 times).

1Cache size/Memory speed info tool 2.65MMX - (c) 1999-2001, LRMS - DJGPP compiled
2CPUID support detected... 'GenuineIntel' with FPU TSC MMX
3Family=5 Model=4 Step=3 Type=0 Chipset (Vendor/Device ID(Rev)): Intel/7100(01)
4CPU clock: 233.9 MHz
5Using 16MB physical memory block (alignment = 32)
6Bandwidth - MMX linear access test... Read/Write/Copy (MB/s)
7Block of     1KB: 1234.5 / 175.0 / 337.9
8Block of     2KB: 1265.3 / 172.0 / 340.0
9Block of     4KB: 1281.3 / 170.5 / 340.0
10Block of     8KB: 1289.4 / 169.9 / 339.2
11Block of    16KB: 1230.3 / 169.6 / 332.6
12Block of    32KB: 239.8 / 169.4 / 226.4
13Block of    64KB: 239.8 / 169.3 / 226.3
14Block of   128KB: 239.9 / 169.3 / 224.0
15Block of   256KB: 239.9 / 169.3 / 226.4
16Block of   512KB: 239.9 / 169.2 / 226.4
17Block of  1024KB: 160.0 / 169.2 / 124.7
18Block of  2048KB: 160.0 / 169.2 / 124.6
19Block of  4096KB: 160.0 / 169.2 / 124.6
20Block of  8192KB: 160.0 / 169.2 / 124.6
21Block of 16384KB: 160.0 / 169.4

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