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First post, by Haz939

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Hello,

I wonder if anyone can help me? I'm trying to essentially build an 486 SBC computer using the SIS85C471 chipset. The computer will interface through a 16 bit ISA interface and will have the bare minimum of components for it to work. The video, sound, serial and IDE drive connections will be from pre-existing ISA cards.

I think I'm off to a good start, however I'm having some confusion on how to implement the bus transceivers (74245) I think I've correctly connected the ones for the SD0 bus and XD0 bus from the datasheet and block diagram. It doesn't give much information or an application note on how they should be connected.

There is also some transceivers for the address bus but I can find no mention in the datasheet on how these should be connected, no enable and dir pins for the 74245 like there is for the data bus. My best guess that these signals must connect to the processor.

This is the part of the datasheet that mentions the control and enable signals for the 74245 transceiver and block diagram.

https://drive.google.com/file/d/1wSpw27KvH5ry … iew?usp=sharing

This is my quite crude eagle schematic:

https://drive.google.com/file/d/1wZNo4Xg030tF … iew?usp=sharing

Link to the full SIS85C471 datasheet.

https://www.datasheets360.com/pdf/805338928285727440

Many thanks for any help 😀

Reply 2 of 11, by Haz939

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Thank you, that makes sense now. However, there doesn't seem to be enough stated address lines (A2-25) to cover all the (SA0-19) to (LA-23) going to the ISA slot. These include the (SA0-1) coming from the 85C471. I'm not sure what the extra lines (LA-20) to (LA-23) would connect to?

Reply 3 of 11, by rasz_pl

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if it was meant to be unidirectional it would specify 240 or 244. ISA bus master and DMA require this bus to be switchable. Direction is controlled by /MASTER pin (184) connected directly to ISA bus.

grab yourself a 460 datasheet and schematic of Samsung system based on it
http://www.bitsavers.org/components/sis/85C460.pdf
http://www.bitsavers.org/pdf/samsung/pc/98134 … Manual_1993.pdf page 119

Open Source AT&T Globalyst/NCR/FIC 486-GAC-2 proprietary Cache Module reproduction

Reply 4 of 11, by SSTV2

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Just checked sis 471 datasheet, rasz_pl is right, in case you are going to implement a bus mastering device, eg. SCSI or ethernet controller into your SBC, then you should make the address bus buffer bidirectional, othervise it can be left unidirectional.

Haz939 wrote on 2021-11-06, 16:29:

Thank you, that makes sense now. However, there doesn't seem to be enough stated address lines (A2-25) to cover all the (SA0-19) to (LA-23) going to the ISA slot. These include the (SA0-1) coming from the 85C471. I'm not sure what the extra lines (LA-20) to (LA-23) would connect to?

I'm not sure if i understood your question correctly, but according to datasheet's block diagrams, address lines before buffers are called A2:23, afterwards their naming scheme splits and changes to SA0:19 and LA17:23, but essentially all of the address lines are still there.

Reply 5 of 11, by Haz939

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rasz_pl wrote on 2021-11-06, 17:48:
if it was meant to be unidirectional it would specify 240 or 244. ISA bus master and DMA require this bus to be switchable. Dire […]
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if it was meant to be unidirectional it would specify 240 or 244. ISA bus master and DMA require this bus to be switchable. Direction is controlled by /MASTER pin (184) connected directly to ISA bus.

grab yourself a 460 datasheet and schematic of Samsung system based on it
http://www.bitsavers.org/components/sis/85C460.pdf
http://www.bitsavers.org/pdf/samsung/pc/98134 … Manual_1993.pdf page 119

Thank you, that was prove very useful in implementing the transceivers, particular this page:

https://drive.google.com/file/d/1aosMS8JbXjl3 … iew?usp=sharing

Last edited by Stiletto on 2021-11-08, 05:32. Edited 1 time in total.

Reply 6 of 11, by Haz939

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SSTV2 wrote on 2021-11-06, 21:07:

Just checked sis 471 datasheet, rasz_pl is right, in case you are going to implement a bus mastering device, eg. SCSI or ethernet controller into your SBC, then you should make the address bus buffer bidirectional, othervise it can be left unidirectional.

Haz939 wrote on 2021-11-06, 16:29:

Thank you, that makes sense now. However, there doesn't seem to be enough stated address lines (A2-25) to cover all the (SA0-19) to (LA-23) going to the ISA slot. These include the (SA0-1) coming from the 85C471. I'm not sure what the extra lines (LA-20) to (LA-23) would connect to?

I'm not sure if i understood your question correctly, but according to datasheet's block diagrams, address lines before buffers are called A2:23, afterwards their naming scheme splits and changes to SA0:19 and LA17:23, but essentially all of the address lines are still there.

It would be nice to use an ethernet controller or SCSI but I may just keep the bus unidirectional for simplicity sake for now.

Sorry if my question was confusing. But to my eyes theirs doesn't seem to be enough address lines to support that many signals out. My picture will show you what I mean.

https://drive.google.com/file/d/1YUfJ6hDh7LIp … iew?usp=sharing

Reply 8 of 11, by Haz939

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SSTV2 wrote on 2021-11-06, 23:30:

I don't get access to google drive links, could you attach images directly to the post?

You should be able to view the link now.

https://drive.google.com/file/d/1YUfJ6hDh7LIp … iew?usp=sharing

Reply 10 of 11, by SSTV2

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In your schematic A[2:23] lines are connected to buffers correctly but at IC6 output you assigned names wrong, starting from IC5 pin 11 and up, pin names should be LA[17:23], then you take another buffer and connect 3 least significant LA lines (17-19) to create 3 most significant SA lines, at least this is how rasz_pl's linked service manual document on page 119 implements ISA address bus.

Reply 11 of 11, by rasz_pl

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>You need access Ask for access, or switch to an account with access.

Network ones dont use DMA (there are ISA network chips with theoretical capability, but I dont know of any cards actually implementing it). IDE controllers dont. SCSI yes, particularly AHA-1540/1542 does bus mastering. Floppy and sound cards use DMA, but 8237 is implemented directly in the chipset and that sits on the CPU side of the bus so shouldnt be a problem with unidirectional buffer.

The best thing you could do would be hunting down a motherboard already using one of SIS 460/471 chipsets - that way you will have a master implementation to compare to and measure live behavior. That Samsung diagram is the second best thing.

Open Source AT&T Globalyst/NCR/FIC 486-GAC-2 proprietary Cache Module reproduction