First post, by migry
So the story is, I have designed and built a 8088 PC compatible PCB, using the standard I/O chip set (8259 ICU, 8253 Timer, 8255 PPI) and I am currently debugging the system. I use SRAM so no need for complicated refresh using DMA. For simplicity I omitted DMA, hoping that I could read the floppy using polled I/O. I then discovered that the Tandy 1000 does just that. I have used a uPD765 as a floppy controller, and after some effort now appears to be working (double density only).
I also put the 8088 into minimum mode, as this simplifies the design, and removes the need for the 8288 bus controller, which is difficult to find (and expensive if found). My understanding is that in minimum mode the 8087 cannot be used. Looking at the original IBM PC design , which puts the 8088 into maximum mode the 8087 connects to the RQ/GT1 of the 8088, and the RQ/GT0 is tied to VCC. Since I have the 8088 in minimum mode, the two RQ/GT pins are HOLD/HLDA which I use to float the CPU in order to load the RAM.
So it appears that the IBM PC does not use the normal CPU float mechanism (HOLD/HLDA or RQ/GT) for DMA. So exactly how is DMA achieved?
The logic associated with WAIT/RDY and DMA is quite complicated, one reason why I decided not to implement DMA. My best guess it that when there is a DMA request, the bus cycle is paused using RDY and tristate buffers remove the CPU from the bus. When the DMA cycle completes, I assume that the paused read/write completes? I do see a signal called "DMA_WAIT" going to the RDY1 pin of the 8284 clock generator, which is why I suspect this mechanism is used to implement a psuedo-DMA. Are there any document with waveforms out there? Seems pretty nasty to me 😉 if so.
I am particularly interested in how floppy DMA works. The best I can figure out is that each byte from the uPD765 FDC uses this mechanism. I note that the DRQ output from the FDC passes through a 4 flop shift register to implement some kind of delay, but why? Looks like the uPD765 (based on an Intel design?) is the only FDC which is suited to the PC DMA mechanism.
I also understand that the floppy DMA uses "fly by" where the FDC read and memory write are asserted at the same time. So I can see how this works to transfer between memory space and I/O space, but can the DMA also do memory to memory transfers, which must use separate read and write cycles.
On the next iteration of my PCB for the 8088 CPU, I was wondering if I could add the DMA controller and page register IC, but simplify the design by using HOLD/HLDA, rather than the read/write pause mechanism (if this is actually the way DMA is done). I'm not interested in adding support for the 8087, although ironically I have 3 of these devices kept from the 80's when rescused from old equipment. I hope to sell them, although I really need to test them first.