Reply 20 of 23, by reenigne
There's a subtle issue with relying on the memory-to-memory copy DMA to do the refresh: suppose the low 8 bits of the refresh address are 0xFE when the memory-to-memory copy starts, and the memory-to-memory copy does a copy from address 0x00-0xFF. The address 0xFF goes unrefreshed for almost twice as long as normal, which would be running it out-of-spec and could cause DRAM decay in some machines. The "sped up refresh" protocol before and after doing anything else with DMA channel 0 avoids this.
Another subtlety is that you can't do anything else with the machine while a memory-to-memory copy is going on: the DMAC forces block mode on when memory-to-memory mode is enabled, so the CPU doesn't get access to the bus again until it completes. So not useful for parallelising a memory fill with non-CPU-bound tasks either I'm afraid!