VOGONS


Reply 20 of 31, by rmay635703

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Anonymous Coward wrote on 2022-01-14, 15:20:

Did ST ever get access to the MII? I only seem to remember them doing up to the 6x86L. I think they got dropped after Cyrix was bought by NatSemi.

You could still buy brand new trays of ST PR166 chips in 2005, I was told they were used in random appliances.

Personally have never noticed anything
ST beyond 6x86 PR200, if the exist in MX form they must be rare or regional

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Reply 21 of 31, by Sphere478

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Okay, I hooked it back up and did some investigation.

It seems that setting bf2 pin results in no post on this chip?!

I have these dip settings on this freeway design motherboard
5, 6, 7
Which I assume correspond to bf0, bf1, bf2 respectively.

So with that ASSUMPTION in hand,
0 = off 1= on
bf0 bf1 bf2
0 0 0 500gp 347mhz
0 0 1 no post
0 1 0 433gp 298mhz
0 1 1 no post
1 0 0 233gp 199mhz
1 0 1 no post
1 1 0 366gp 249mhz
1 1 1 no post

Tests were done at 100fsb. To reach other gp pr ratings it is assumed adjusting the bus clock is required.

So in summary, it seems that the chip supports 3.5x, 3x, 2.5x, and 2x.

Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
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SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
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Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 22 of 31, by Sphere478

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One final remark, the processor is really fast in windows, boots very fast. Very responsive. In many things it acts like it has performance comparable to a equally clocked k63+ Which is impressive. But alas, this chip isn’t stable at 350mhz and at 300 it is a far cry from the performance of a k63+ running at 600mhz.

I can actually play halo on the k63+, but the cyrix, forget it.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 23 of 31, by BitWrangler

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I would have investigated BF2 settings at lower bus speeds, 66 or lower if possible, I believe the BF2 settings should be 4x, 4.5x and 5x at least.

Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.

Reply 24 of 31, by Sphere478

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BitWrangler wrote on 2022-01-14, 19:01:

I would have investigated BF2 settings at lower bus speeds, 66 or lower if possible, I believe the BF2 settings should be 4x, 4.5x and 5x at least.

That’s a good idea, good catch one sec, lemme test,

Last edited by Sphere478 on 2022-01-14, 19:18. Edited 1 time in total.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 25 of 31, by Sphere478

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66 mhz bus test

0= off 1= on
bf0 bf1 bf2
0 0 0 500gp 347mhz 100fsb
0 0 1 100fsb no post 66fsb no post
0 1 0 433gp 298mhz 100fsb
0 1 1 100 fsb no post 66fsb no post
1 0 0 233gp 199mhz 100fsb
1 0 1 100fsb no post 66fsb 333gp 266mhz
1 1 0 366gp 249mhz 100fsb
1 1 1 100fsb no post 66fsb 333gp 266mhz

So there we go, there is the 4x setting!

Last edited by Sphere478 on 2022-01-14, 19:26. Edited 6 times in total.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 26 of 31, by snufkin

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Just had a go at looking some of this up, which seems to match with what you've found.

Mii datasheet I looked at had pins y33, x34 and w35 being ckmul0, ckmul1 & reserved. In a later addendum it listed w35 as ckmul2. So same pins as Intel bf0,bf1,bf2. It also gave some model numbers with speed (with the MII400 from the addendum):

model     mult   bus   CPU
MII-300GP x3 75MHz 225MHz
MII-300GP x3.5 66MHz 233MHz
MII-333GP x2.5 100MHz 250MHz
MII-350GP x3 100MHz 300MHz

MII-400GP x3 95MHz 285MHz

But no actual table showing ckmul settings and multiplier (found one for other chips in a thread about earlier versions: Subtle differences between Cyrix and IBM 6x86s ). Flicking through some pictures of the MII I can see chips labelled as 2.5x,3x,3.5x and 4x. So at least some versions went higher than 3.5x.

[edit: Ah, found a table here: https://www.pchardwarelinks.com/cpuspeed.htm
that says the highest for the MII was x4 on some versions]

Reply 27 of 31, by Sphere478

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snufkin wrote on 2022-01-14, 19:11:
Just had a go at looking some of this up, which seems to match with what you've found. […]
Show full quote

Just had a go at looking some of this up, which seems to match with what you've found.

Mii datasheet I looked at had pins y33, x34 and w35 being ckmul0, ckmul1 & reserved. In a later addendum it listed w35 as ckmul2. So same pins as Intel bf0,bf1,bf2. It also gave some model numbers with speed (with the MII400 from the addendum):

model     mult   bus   CPU
MII-300GP x3 75MHz 225MHz
MII-300GP x3.5 66MHz 233MHz
MII-333GP x2.5 100MHz 250MHz
MII-350GP x3 100MHz 300MHz

MII-400GP x3 95MHz 285MHz

But no actual table showing ckmul settings and multiplier (found one for other chips in a thread about earlier versions: Subtle differences between Cyrix and IBM 6x86s ). Flicking through some pictures of the MII I can see chips labelled as 2.5x,3x,3.5x and 4x. So at least some versions went higher than 3.5x.

[edit: Ah, found a table here: https://www.pchardwarelinks.com/cpuspeed.htm
that says the highest for the MII was x4 on some versions]

Sweet!

Thx!

Okay: so I suppose I can simplify this further with a condensed table

1= on 0 = off
Bf0, bf1, bf2
1 0 0 = 2x
1 1 0 = 2.5x
0 1 0 = 3x
0 0 0 = 3.5x
1 0 1/ 1 1 1 = 4x

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 28 of 31, by Sphere478

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Gonna see if I can decode the multiplier options for a 2.9v 366 now.

1=on 0=off

(66fsb test actual mhz, not PR)

Bf0, bf1, bf2
0, 0, 0 233mhz 3.5x
1, 0, 0 133mhz 2.0x
0, 1, 0 200mhz 3.0x
1, 1, 0 166mhz 2.5x
0, 0, 1 66.7mhz 1.0x (otherwise known as 8ghz)
1, 0, 1 266mhz 4.0x
0, 1, 1 66.7mhz 1.0x (otherwise known as 8ghz)
1, 1, 1 266mhz 4.0x

Attachments

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 29 of 31, by BitWrangler

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Hahaaaaa, post screenies to HWBot 🤣

Unicorn herding operations are proceeding, but all the totes of hens teeth and barrels of rocking horse poop give them plenty of hiding spots.

Reply 30 of 31, by Sphere478

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BitWrangler wrote on 2022-03-12, 04:45:

Hahaaaaa, post screenies to HWBot 🤣

Hehehe. I found that quite amusing 🤣

What would be the other cores that I need to test to find their multis? Is the next one the 3.3v cores or was there a revision between the 366 and the 166? That may have a different multi set?

But then again, those cpus probably use the same settings as the 366 but just drop 4x

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)