First post, by Paul_V
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UPD: I'm in the process of removing outdated/irrelevant info for the ease of reading.
Hello, everyone and happy holidays.
For a couple of months now I've been tinkering with a Vortex86DX boards to use for a retro rig.
While the rig is yet far from completion, I've gathered a bunch of info and personal findings, which I have not found posted elsewhere and decided to share.
I'll try to add info as the progress goes.
1) BIOS
Vortex86DX is basically a SoC, it can be crossflashed to almost any BIOS written for it, provided it has the nessesary videocard chip BIOS rom.
I have succesfully cross-flashed PCM-3343 (Which has AWARD bios with no disable L1\L2 cache capability) with AMI bios from PFM-535S, which share the same Lynx EM+ GPU.
You can also swap the GPU ROM modules with AWARD BIOS 6.0 \ AMIBIOS8 proprietary tools (e.g. to replace fixed resolution LCD rom with CRT)
I DO NOT RECOMMEND tinkering that way if you don't know what you're doing.
BIOS chip is integrated in the CPU itself, and in the case of failure you won't be able to recover without proprietary software and cabling.
All boards I own have proprietary JTAG connector to flash the BIOS, requiring a parallel xilinx cable and proprietary jflash.exe utility.
I've been using BIOSMP.exe utility from DM&P to flash and dump SoC BIOS with no issues so far.
2) CLOCK DIVIDER, CACHE REGISTERS, PLL LIMITATIONS:
CLOCK DIVIDER:
The PLL Clock divider register is well documented here (North Bridge Fun 0, Offset A0h, bits 0-2)
http://www.dmp.com.tw/tech/DMP_Vortex86_Serie … ence_091216.pdf
PLL Clock division can be set to 1/2/3/4/5/8/16 or 32. Datasheets mention some older revisions which may have 1/2/3/4/5/6/7 or 8
Can be changed on the fly with any PCI register editor or debug.
CACHE REGISTERS:
L1 Cache can be disabled from BIOS or by using existing x86 cache disabling utilities (CR0 register bit 30)
L2 Cache can be disabled from BIOS or by editing NorthBridge register:
North Bridge Function 1
Register Name: L2 Cache Control Register
Register Offset: E8h bits 0-1
BIT 1: L2 Cache Write back enable
0: write through
1: write back
BIT 0 :L2 Cache enable
0: disable
1: enable
DIVIDER PLL LIMITATIONS:
(Confirmed by ICOP)
Disabling L1 Cache effectively disables any PLL CPU division on DX/DX2/DX3.
(In practice DX can still use /2 division, but any value below that won't work)
Also, SoC cannot clock lower than it's current PCI bus speed.
3) CPU and DDRII HARDWARE CLOCK STRAPS
If cache disable and clock division options aren't enough for you, then it's time to dig deeper in the datasheets.
There are hardware straps on the SoC itself that you can use to set initial CPU\RAM frequency.
Two different datasheets can be found on the internet for the SoC. The first one in my case got the wrong data on the straps (maybe the were several revisions of CPU, idk)
The link below is what worked on my PCM-3343
https://www.vortex86.com/file?serial=Vortex86 … a_sheet_V200_BF
I've attached a brief table with strap configuration (does not cover all possible cpu values), as well as the location of the straps for the PCM-3343 (pins location on the CPU itself can be seen in datasheet)
The CPU pins for setting CPU clock are : C11,B12,B11
For setting RAM clock, the CPU pins are: A12, C10
A strap pin pulled-down with 4.7k resistor to GND is "0"
A strap pin pulled-up with 4.7k resistor to 1.8v VCC is "1"
No pull-up or pull-down on a pin is a tri-state "z"
For a different motherboard, you'll have to locate these pins and traces manually.
The traces may not even exist, if the manufacturer didn't need\design them, but there's a trick to identifying them:
1) Most of these strap resistors share the same pins on DX with RAM ICs. (e.g. MA10 strap elecrically share the same trace with RAM IC A10 pin, check with the datasheet).
2) Having a board with SoC\RAM frequency other than 800\400Mhz means there are definitely some strap resistors present.
The cross-flashed BIOS I got also had a hidden option "DDRII power saving" and DDR timings. It cuts the bandwidth of the RAM by about 25%
UPD 22.02.22:
Hardware strap info, benchmarks and other data will be poster and updated here:
https://docs.google.com/spreadsheets/d/1wEa2x … dit?usp=sharing
