VOGONS


First post, by Paul_V

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Hello, everyone and happy holidays.

For a couple of months now I've been tinkering with a Vortex86DX boards to use for a retro rig.
While the rig is yet far from completion, I've gathered a bunch of info and personal findings, which I have not found posted elsewhere and decided to share.
I'll try to add info as the progress goes.
Also, a couple of questions I'm hoping someone would kindly be able to answer.

1) BIOS
First thing is rather obvious: as Vortex86DX is basically a SoC, it can be crossflashed to any BIOS written for it, provided it has the nessesary videocard rom in it.
I have succesfully cross-flashed PCM-3343 (Which has AWARD bios with no disable L1\L2 cache capability) with AMI bios from PFM-535S, which share the same Lynx EM+ GPU.
A big leap of faith from my part, however. And I certanly DO NOT RECOMMEND tinkering that way. BIOS chip is integrated in the CPU itself, and in the case of failure you're practically screwed.
All boards I own have JTAG to flash the BIOS, but I've yet to recieve a programmer to try tinkering with it, but my expectations are not high.

2) CLOCK DIVIDER and CACHE weirdness
The clock divider register was easy, as it's well documented here (North Bridge A0h bits 0-2)
http://www.dmp.com.tw/tech/DMP_Vortex86_Serie … ence_091216.pdf

Can be changed on the fly, and that's where the interesting stuff happened.
All datasheets mention division from 1 to 8, while the BIOS and north bridge registers offer 1/2/3/4/5/8/16/32
x8 division with all cache disabled performs almost exactly as x32 (cache\ no cache option doesn't matter if x32 is chosen - the performance is the same).
I'm fairly positive that x16 \ x32 division option is conditional and something else is done (like cache flush or disable) to throttle the cpu.
Traditional bechmark tools and games results are so erratic i'm unable yet to put this theory on solid ground.

As for the cache, most tools detect only L1.
L2 can be disabled from BIOS (that's why I decided to cross-flash my board, to get the option)
Other than that, my knowledge of low level programming is limited: if someone could write a programm that could detect both L1\L2 cahce and disable them as needed, that would be awesome
By the way - L1 on this cpu is divided to 16K-I cache and 16K-D cache. Whether BIOS disables them both is a good question
Speed sensitive games sometimes act wierd to cache disable - first few seconds it's "Pedal to the metal", then comes to normal speed. I couldn't find any power management features, so I believe it may be due to separated L1 caches.

3) CPU and DDRII HARDWARE CLOCK STRAPS
The sweetest of them all, the dreaded multi-tool "turbo-button to catch switch them all". And in my case also in the form of soldering 0402 smd resistors (all good things come in small packages, eh?)
A little background first: I have two games, which happen to be my personal "retro-rig downclock seal of approval". It's ZanyGolf (DOS port) and Planet's Edge (apart from Privateer, I have not played any wing commander series)
Both are highly clock dependent and you have to downclock pretty low to be able to play them comfortably.
And that's where cache disable and clock division options just weren't enough. It was time to dig deeper in the datasheets.
Turns out, the are hardware straps on the CPU itself, that you can use to choose the cpu and ram clocks.
There are two different datasheets on the internet for the cpu. The first one in my case got the wrong data on the straps (maybe the were several revisions of cpu, idk)
The link below is what worked on my PCM-3343
https://www.vortex86.com/file?serial=Vortex86 … a_sheet_V200_BF

I've attached a brief table with strap configuration (does not cover all possible cpu values), as well as the location of the straps for the PCM-3343 (pins location on the CPU itself can be seen in datasheet)
The CPU pins for setting CPU clock are : C11,B12,B11
For setting RAM clock, the CPU pins are: A12, C10
For a different motherboard, you'll have to locate theese pin's traces manually. The traces may not even exist, if the manufacturer didn't need\design them.

A strap pin pulled-down with 4.7k resistor to GND is "0"
A strap pin pulled-up with 4.7k resistor to 1.8v VCC is "1"
No pull-up or pull-down on a pin is a tri-state "z"

I considered soldering one resistor at a time and checking the results, testing 3 different CPU speeds in the process. Success! But now i'm a puzzled owner of a 500Mhz board.
Lowering the CPU clock from 800Mhz to 500Mhz did not help much. While SPEEDSYS shows ridiculous low numbers on lowest settings (score of 5.69), it's still too fast for Planet's Edge.

Now it seems obvious - I have to downclock RAM. Vortex CPU is throttled by it's own clock divider, leaving it's bus speeds intact.
300mhz DDRII is blazingly fast for DOS-era stuff. The cross-flashed BIOS I got had a hidden option "DDRII power saving". I don't know what exactly it does, but it cuts the bandwidth of the RAM by about 25%
Planet's Edge is now playable, but barely (still a bit fast). Looks like i'll need to solder another strap to lower the DDR clock, but I'm reluctant to do so yet.
I'm afraid it will cripple the system to the point that I will be unable to achieve a comfortable performance in Nascar Racing.

So, summing this up:
Would someone be interested in developing a tool or adding support to existing one to control this cpu's registers in term of clock control and L1-I\L1-D\\L2 caches?
I'm willing to make any test necessary on my part.

UPD 22.02.22:
Hardware strap info, benchmarks and other data will be poster and updated here:
https://docs.google.com/spreadsheets/d/1wEa2x … dit?usp=sharing

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Last edited by Paul_V on 2022-02-22, 20:16. Edited 13 times in total.

Reply 1 of 18, by snufkin

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Paul_V wrote on 2021-12-29, 17:13:
1) BIOS First thing is rather obvious: as Vartex86DX is basically a SoC, it can be crossflashed to any BIOS written for it, pro […]
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1) BIOS
First thing is rather obvious: as Vartex86DX is basically a SoC, it can be crossflashed to any BIOS written for it, provided it has the nessesary videocard rom in it.
I have succesfully cross-flashed PCM-3343 (Which has AWARD bios with no disable L1\L2 cache capability) with AMI bios from PFM-535S, which share the same Lynx EM+ GPU.
A big leap of faith from my part, however. And I sertanly DO NOT RECOMMEND tinkering that way. BIOS chip is internal in this thing, and in the case of failure you're practically screwed.
All boards I own have JTAG to flash the BIOS, but I've yet to recieve a programmer to try tinkering with it, but my expectations are not high.

Just wondering if an external EEPROM can be used for the BIOS. The datasheet you linked says "The Flash could be disable & use external Flash ROM" and there's a Q&A on the Vortex86SX that says "You can use external flash as the BIOS storage, for example SST 39SF020-90-4C-PH, please pull-down the Hardware Strap MA12 and MA13 to enable the external BIOS flash.", from here: https://www.dmp.com.tw/tech/vortex86sx/faq.htm#1005

The pinout datasheet for the 86DX you linked to has pin F10 as Strap[12], defaults to internal pull up (BIOS on internal SPI), pull low for 8-bit flash, and pin G21 is a ROM chip select pin which might be involved (but might be to with boot ROM rather than BIOS).

Unfortunately it doesn't seem to give any more information about how to connect an external ROM. Given they won't give any information about the JTAG programming interface then they probably won't help with this either.

All seems like a lot of work with a lot of guesses so no great expectation of it working.

I did find what looks like am more complete datasheet for the 86EX in case it's any use, but it seems to get it's BIOS from the PCI bus:
https://www.86duino.com/wp-content/uploads/20 … V14_86duino.pdf

1. High BIOS Area (FF00_0000–FFFF_FFFFh) The top 16 Mbytes of the Extended Memory Region is reserved for System BIOS (High BIOS) […]
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1. High BIOS Area (FF00_0000–FFFF_FFFFh)
The top 16 Mbytes of the Extended Memory Region is reserved for System BIOS (High BIOS),
extended BIOS for PCI devices, and the A20 alias of the system BIOS. The CPU begins execution
from the High BIOS after reset. This region is mapp ed to the PCI so that the upper subset of this
region is aliased to 16 Mbytes minus 256 Kbytes range.

Reply 2 of 18, by Mumak

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I have been working with these systems a couple of years ago for a company I worked for. Have some datasheets but most are watermarked, so can't release them.
There are also BIOS images (for VDX-6390 EVB) and other design stuff like sch... Not sure what would be of interest here.

Reply 3 of 18, by Paul_V

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snufkin wrote on 2021-12-29, 21:26:
Just wondering if an external EEPROM can be used for the BIOS. The datasheet you linked says "The Flash could be disable & use […]
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Just wondering if an external EEPROM can be used for the BIOS. The datasheet you linked says "The Flash could be disable & use external Flash ROM" and there's a Q&A on the Vortex86SX that says "You can use external flash as the BIOS storage, for example SST 39SF020-90-4C-PH, please pull-down the Hardware Strap MA12 and MA13 to enable the external BIOS flash.", from here: https://www.dmp.com.tw/tech/vortex86sx/faq.htm#1005

The pinout datasheet for the 86DX you linked to has pin F10 as Strap[12], defaults to internal pull up (BIOS on internal SPI), pull low for 8-bit flash, and pin G21 is a ROM chip select pin which might be involved (but might be to with boot ROM rather than BIOS).

Unfortunately it doesn't seem to give any more information about how to connect an external ROM. Given they won't give any information about the JTAG programming interface then they probably won't help with this either.

All seems like a lot of work with a lot of guesses so no great expectation of it working.

Vortex86SX supports 16-bit flash, while Vortex86DX supports only 8bit, while having 16-bit flash integrated. DM&P support claims almost no one uses external SPI for BIOS.
PCM-3343 does have an unsoldered pads for external spi flash along with some missing components, but I was unable to locate the traces for the strap that switches the cpu to use external chip (had to resort to services of an x-ray machine to find cpu\ram strap traces). And I honestly don't know if 16-bit and 8-bit BIOS chips are interchangeble. This external chip is mostly used as a virt. floppy boot device.
Considering JTAG, I'm quite sure it's wiggler-type parallel interface cable. The only question is the utulity used for flashing. And the company, which mentioned "jflash" utility in their manual is, unfortunately, long gone.
Advantech has a couple of similar utilities, for the intel StrongARM and Xscale based cpus. A pretty long shot, but i'll try to tinker more, when I find time to bodge a parallel cable.
Until then, I'm pretty limited on the amount of experiments I can do on the BIOS. Pushed my luck pretty hard twice already.
https://www.advantech.com/support/details/manual?id=1-DDI4J

Mumak wrote on 2021-12-29, 22:00:

I have been working with these systems a couple of years ago for a company I worked for. Have some datasheets but most are watermarked, so can't release them.
There are also BIOS images (for VDX-6390 EVB) and other design stuff like sch... Not sure what would be of interest here.

If you could provide a dump, I would be most grateful. Vortex86 BIOSes are hard to come by. They also often have a ton of hidden options.
I'm currently awaiting VDX-6354RD to play with and to compare.

Reply 6 of 18, by Paul_V

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Apart from having different external LAN rom and less hidden options, VDX-6390 BIOS seems almost identical to the AMI BIOS the PFM-535S has (PFM-535S has more options, but they are useless in terms of underclocking).
I think most of the Vortex86DX OEM motherboard manufactures have just been swapping these roms with minimal modifications, hiding unnecesary options, with the exception being Advantech with their own AWARD 6.00PG BIOS
I've found a reference manual for the AMI BIOS, which covers almost all capabilities (with the exception of north bridge options and some others).
Interestingly, the manual clearly shows CPU divisions from 1 to 8, so there's definitely been a SoC revision change, as the division is controlled by the north bridge register.

http://ftp.emacinc.com/LegacyProducts/S ... _v1r0A.pdf

Also, AWARD BIOS makes utility like FDAPM detect APM 1.2 cabablities, while AMI not.
The only half-working options FDAPM could do is enter suspend and stanby, which it could not not wake up from. No luck throttling this way yet.

The best downclock results so far, which make Planet's Edge somehow playable:
500Mhz CPU strap with /8 divider = 62,5Mhz (/32 divider makes no difference, apart from making BIOS menu keystroke lags)
L1/L2 disable
Unlocked AMI BIOS option - DDRII Power Saving Mode (Active/Precharge)

I've soldered an additional pull-down resistor to downclock RAM from 300Mhz to 266Mhz and updated results in the first post.
The results are negligible at best. I have a feeling i'm missing on something.
In theory, i'm still about 30Mhz away from the absolute minimum this CPU can operate. In datasheet, there is a note that a CPU cannot clock lower than it's bus speed, which is 33Mhz. And this is the indirect proof that /16 and /32 dividers do something else. 800/32= 25Mhz, which is well below that threshold. Makes me wonder if overclocking the CPU to 1066Mhz and then choosing /32 option will work any different (probably not, as x16 on a 800Mhz did not result in 50Mhz by timestamp measurement).

Anyway, from now on I'll need to find a way of reliably soldering some wires or connectors to the tiny 0402 pads without fearing them being torn in the process.
Otherwise, constant resoldering and reconnecting will put too much stress on the board.

Last edited by Paul_V on 2022-01-09, 22:31. Edited 3 times in total.

Reply 7 of 18, by Paul_V

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I've got my hands on a ebox-3300 mobo and have successfully identified CPU and RAM straps on it (R5/R6; R7/R8; R9/R10; R11/R12; R13/R14 - are the pullup/pulldown resistors on the mobo, I'll post more details later).
It defaults at 933Mhz CPU and 300Mhz RAM. (This configuration requires a total of three pull-down straps, which made identifying them much easier)
It has more soldering-friendly 0602 type smd pads, so I think I'll use this motherboard to solder test switches and run benchmarks.
It does not qualify for me as a retro-rig due to the absence of an ISA(PC/104) slot, but can provide tons of useful data .
I've already begun identifying which straps are for CPU and which are for RAM. I've pulled R5/R6 high by soldering 4.7k to R5.
It turned to be STRAP-4 for RAM, which downclocked it from 300Mhz to 166Mhz, perfectly matching the datasheet.

Switching RAM to 166Mhz and applying all other downclocking vo0doo stuff on a default 933Mhz CPU strap setting, I was able to achieve a score of 49 in TOPBENCH.
Even Wing Commander runs somehow sluggish now.

There's also another pitfall with BIOS flash utilities.
To unlock some options, I've dumped original ebox-3300 BIOS using BIOSMP (original DMP utility) and SPIFLASH (which was in the archive with BIOS kindly provided by Mumak).
The sheer volume of the BIOS chip is 2MB (hence, the dump is also 2MB), but the BIOS image itself is 256KB.
2MB dump is uneditable in AMIBCP, so I had to manually cut empty space of the dump in hex editor for it to match.
Moreover, SPIFLASH dumped only empty space, which resulted in a 1835008KB dummy file filled with FF's.
Pushed my luck once more, now I have all the options I need.

Currently, I'm filling a table with benchmark results using TOPBENCH.
Some stuff turns out to be pretty interesting. I'll publish the results when I complete all possible combinations with this motherboard.
Here's the short summary of currently available options on Vortex86DX, making it the most versatile hardware piece I've ever had:
1) HW straps to clock CPU from 500Mhz to 1000Mhz (may be lower/higher, but needs testing. datasheet mentions speed sync to RAM and clocks up to 1500Mhz)
2) HW straps to clock RAM from 166Mhz to 400Mhz
3) L1/L2 Cache (L2 cache control currently available only as an AMI BIOS option, no utility yet)
4) CPU clock division 1/2/3/4/5/6/8 (/16 and /32 division usefulness are questionable at the moment - I have theories and need more tests.)
5) DDR II Power Saving Modes Active\Prefetch
6) Memory timings (CAS range from 2 to 5 CLKs; tWR from 1 to 7 CLKs;tRP from 1 to 15 CLKs; tRCD from 1 to 15 CLKs)

P.S.
Setting RAM speed to 166Mhz did not seem to cripple Nascar Racing 1\2 performance very much.
So soldering just the resistors as the final solution for the versatile retro-rig is still a viable option.
Don't want to end up with a retro-rig dosbox sim with a ton of switches.

Last edited by Paul_V on 2022-01-10, 09:19. Edited 6 times in total.

Reply 8 of 18, by debs3759

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Paul_V wrote on 2022-01-09, 22:19:

The sheer volume of the BIOS chip is 2Mb (hence, the dump is also 2Mb), but the BIOS image itself is 256kb.

Did you mean 2Mb and 256KB? 2Mb = 256KB. Small b is bits, large B is bytes.

See my graphics card database at www.gpuzoo.com
Constantly being worked on. Feel free to message me with any corrections or details of cards you would like me to research and add.

Reply 9 of 18, by Paul_V

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debs3759 wrote on 2022-01-09, 23:18:
Paul_V wrote on 2022-01-09, 22:19:

The sheer volume of the BIOS chip is 2Mb (hence, the dump is also 2Mb), but the BIOS image itself is 256kb.

Did you mean 2Mb and 256KB? 2Mb = 256KB. Small b is bits, large B is bytes.

Sorry, my bad. I mistyped the values, it's MB and KB, of course. The flash chip is 2MB and the BIOS image is 256KB. I'll make corrections to the post above

Reply 10 of 18, by debs3759

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It's an easy mistake. I didn't always know there was a difference 😀

See my graphics card database at www.gpuzoo.com
Constantly being worked on. Feel free to message me with any corrections or details of cards you would like me to research and add.

Reply 11 of 18, by Paul_V

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Some preliminary results:
I've chosen Topbench as a primary reference tool, Doom min\max benchmark from Phil's benchmark compilation as a secondary reference and internal timestamp counter from chkcpu beta.
The particular interest is the behaviour of the CPU (or I should better start calling it SoC), which is counter-intuitive. (I've omitted the rest of BIOS settings benchmarks on the screenshot for the time being)
CPU divider setting works "almost" as intended, while the L1 cache is on. (I'm still positive, that timestamp counter will show adequate numbers on bothD/16 and D/32 if I overclock the CPU to 1066Mhz first).

But, as soon as L1 is disabled, all divider settings below D/2 become negligible, or have no effect at all. 0_o

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Reply 12 of 18, by Paul_V

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Small update:
A link to a document (containing hardware stap info, benchmarks, etc), which I'll be updating as I go.
https://docs.google.com/spreadsheets/d/1wEa2x … dit?usp=sharing

Current progress is somewhat slow due to various reasons and I'm yet to devise a way of safely soldering hardware strap switch.

Reply 13 of 18, by Paul_V

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A small update concerning BIOS and motherboard un-bricking:

Eventually, I was able to boot from external ISA\EEPROM 8bit flash BIOS.
The main trick is that the SoC pin 'F10', which you need to pull low is also an address pin A12 of the DDR2 memory ICs.
A12 is easily accessible due to it being on the outside (see pic below, I inserted a cable between A12 and NC ball pins VERY CAREFULLY, as the Vdd pin is nearby and used a 10k pull-down resistor). Moreover, if your motherboard does have some unsoldered memory IC's pads, it becomes even easier.

I've made a simple pc/104(ISA) to EEPROM adapter, flashed a 29EE020 chip with AMI Bios
Then, pulled the A12 low (any memory chip will do, as these pin runs in parallel).

But now I found myself in a predicament. I cannot seem to flash internal SPI flash when having system booted from ISA.
The only difference I could find is PCI register 61h, which is read-only and not listed in datasheet.
I'll try some other tools, but it seems that internal SPI is disabled for good when booting from ISA.
So, this method may not be viable in terms of restoring the original BIOS... bummer. 🙁

Also, I'm somewhat disappointed in a way AMIBIOS8 has been implemented on these boards. AMIBIOS Core 8 bootblock has at least four methods of recovering main bios block: floppy\ATAPI\USB\Serial.
None of them are implemented on ICOP boards. Others have floppy recovery working, probably just because it's a default option they did not turn off when building an image.
Floppy recovery on my boards is useless, as they do not have floppy connector (some others do have a floppy implemented through external super i/o chip)
Besides, onboard sketchy floppy SPI emulation makes recovery procedure think a floppy is already present and tries to search for BIOS file in a void.
All I could do is connect external SPI and format it using SPITOOL.
But could not mount it as a floppy nor copy BIOS file to it. Probably lacking the proper driver in BIOS.

But a least now I'm somewhat able to experiment with BIOS freely without giving everything "RMA seal of approval".

UPD:
Some BIOS'es seem to corrupt the image by overwriting some area with data after first boot if I let the bus handle OE# and WE# signals of the chip.
If I put the chip manually in read-only mode, everything's fine.
My theory is that some BIOS'es save data into FRAM or similar (Both Advantech AWARD and EBOX AMI version have an option to save settings, which persist even without a battery)
So, when you disable SPI and boot from ISA using exact same BIOS image, it probably corrupts itself trying to write data to the wrong address.

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Reply 15 of 18, by Paul_V

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componentswitcher wrote on 2022-05-08, 20:09:

wait so you added isa, could you add a sound card then?

I did not "add" an ISA slot, so to speak. I merely switched the board to seek BIOS code on it's ISA bus, instead of SPI.
The board itself already has an ISA slot implemented, just in another form-factor (PC/104)

So, yes. The sound card (and any other ISA device) can be added, either using diy or industrial PC/104-to-ISA adapter, or designing your own PC/104 format sound card.
Which has already been done by many.
But if you meant that i've used up a slot, which could be used for a soundcsard it's not a problem either. You can stack these either at the bottom or on the top side of the PC104 socket.
A very crude implementation of the adapter below, but it works and gave me alot of insight on this SoC. Additional BIOS chip can easily be added on top of the board in this buid.
My half-failed barbaric Vortex86DX mini retro-pc build

Reply 16 of 18, by rasteri

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Paul_V wrote on 2021-12-29, 17:13:

if someone could write a programm that could detect both L1\L2 cahce and disable them as needed, that would be awesome

Are you still looking for a tool like this? I'm about to do some more vortex86 experiments and will develop such a tool if it's still necessary.

I want to build a (probably) launchbox-based system to run different games and it would be useful to be able to adjust performance settings on a per-game basis.

I can't find any info about the cache registers in any datasheets but I have ICOP's ear so I might be able to find out what they are.

Reply 17 of 18, by Paul_V

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rasteri wrote on 2022-05-15, 14:06:
Are you still looking for a tool like this? I'm about to do some more vortex86 experiments and will develop such a tool if it's […]
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Paul_V wrote on 2021-12-29, 17:13:

if someone could write a programm that could detect both L1\L2 cahce and disable them as needed, that would be awesome

Are you still looking for a tool like this? I'm about to do some more vortex86 experiments and will develop such a tool if it's still necessary.

I want to build a (probably) launchbox-based system to run different games and it would be useful to be able to adjust performance settings on a per-game basis.

I can't find any info about the cache registers in any datasheets but I have ICOP's ear so I might be able to find out what they are.

Hi, rasteri! Thanks for stopping by )

I had an idea to find that register by comparing debug utility output of CPU's registers with cache turned on\off in BIOS, then making a simple batch file.
Never did try it though, as the cross-flashed AMI BIOS with unlocked options did cover almost all of my needs.
Still, this SoC is pretty darn fast for some games even with all my performance crippling voodoo.

The things that bugs me the most by now is JTAG BIOS flashing.
I planned to try something like openocd, but currently lacking free time to do so.

Reply 18 of 18, by Paul_V

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Small update.
I'm uploading a brief schematic on how to connect and boot from ISA EEPROM, in case someone would need it.
Note, that there are some complications using original BIOS image meant for SPI.

I spent some time trying to underclock this SoC further with mixed results.
When using strap option mentioned in the datasheet "SYN DISABLE. CPU clock same as DDR", the board BIOS POST fine and detects all drives,
but is unable to boot from any of them, ending with just a blinking underscore. I observed similar behavior trying running CPU at 1066Mhz

Maybe I'm missing a step there, or maybe it's just a sketchy datasheet and that strap configuration was never meant to be used.

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