First post, by Paul_V
Hello, everyone and happy holidays.
For a couple of months now I've been tinkering with a Vortex86DX boards to use for a retro rig.
While the rig is yet far from completion, I've gathered a bunch of info and personal findings, which I have not found posted elsewhere and decided to share.
I'll try to add info as the progress goes.
Also, a couple of questions I'm hoping someone would kindly be able to answer.
First thing is rather obvious: as Vortex86DX is basically a SoC, it can be crossflashed to any BIOS written for it, provided it has the nessesary videocard rom in it.
I have succesfully cross-flashed PCM-3343 (Which has AWARD bios with no disable L1\L2 cache capability) with AMI bios from PFM-535S, which share the same Lynx EM+ GPU.
A big leap of faith from my part, however. And I certanly DO NOT RECOMMEND tinkering that way. BIOS chip is integrated in the CPU itself, and in the case of failure you're practically screwed.
All boards I own have JTAG to flash the BIOS, but I've yet to recieve a programmer to try tinkering with it, but my expectations are not high.
2) CLOCK DIVIDER and CACHE weirdness
The clock divider register was easy, as it's well documented here (North Bridge A0h bits 0-2)
http://www.dmp.com.tw/tech/DMP_Vortex86_Serie … ence_091216.pdf
Can be changed on the fly, and that's where the interesting stuff happened.
All datasheets mention division from 1 to 8, while the BIOS and north bridge registers offer 1/2/3/4/5/8/16/32
x8 division with all cache disabled performs almost exactly as x32 (cache\ no cache option doesn't matter if x32 is chosen - the performance is the same).
I'm fairly positive that x16 \ x32 division option is conditional and something else is done (like cache flush or disable) to throttle the cpu.
Traditional bechmark tools and games results are so erratic i'm unable yet to put this theory on solid ground.
As for the cache, most tools detect only L1.
L2 can be disabled from BIOS (that's why I decided to cross-flash my board, to get the option)
Other than that, my knowledge of low level programming is limited: if someone could write a programm that could detect both L1\L2 cahce and disable them as needed, that would be awesome
By the way - L1 on this cpu is divided to 16K-I cache and 16K-D cache. Whether BIOS disables them both is a good question
Speed sensitive games sometimes act wierd to cache disable - first few seconds it's "Pedal to the metal", then comes to normal speed. I couldn't find any power management features, so I believe it may be due to separated L1 caches.
3) CPU and DDRII HARDWARE CLOCK STRAPS
The sweetest of them all, the dreaded multi-tool "turbo-button to
catch switch them all". And in my case also in the form of soldering 0402 smd resistors (all good things come in small packages, eh?)
A little background first: I have two games, which happen to be my personal "retro-rig downclock seal of approval". It's ZanyGolf (DOS port) and Planet's Edge (apart from Privateer, I have not played any wing commander series)
Both are highly clock dependent and you have to downclock pretty low to be able to play them comfortably.
And that's where cache disable and clock division options just weren't enough. It was time to dig deeper in the datasheets.
Turns out, the are hardware straps on the CPU itself, that you can use to choose the cpu and ram clocks.
There are two different datasheets on the internet for the cpu. The first one in my case got the wrong data on the straps (maybe the were several revisions of cpu, idk)
The link below is what worked on my PCM-3343
https://www.vortex86.com/file?serial=Vortex86 … a_sheet_V200_BF
I've attached a brief table with strap configuration (does not cover all possible cpu values), as well as the location of the straps for the PCM-3343 (pins location on the CPU itself can be seen in datasheet)
The CPU pins for setting CPU clock are : C11,B12,B11
For setting RAM clock, the CPU pins are: A12, C10
For a different motherboard, you'll have to locate theese pin's traces manually. The traces may not even exist, if the manufacturer didn't need\design them.
A strap pin pulled-down with 4.7k resistor to GND is "0"
A strap pin pulled-up with 4.7k resistor to 1.8v VCC is "1"
No pull-up or pull-down on a pin is a tri-state "z"
I considered soldering one resistor at a time and checking the results, testing 3 different CPU speeds in the process. Success! But now i'm a puzzled owner of a 500Mhz board.
Lowering the CPU clock from 800Mhz to 500Mhz did not help much. While SPEEDSYS shows ridiculous low numbers on lowest settings (score of 5.69), it's still too fast for Planet's Edge.
Now it seems obvious - I have to downclock RAM. Vortex CPU is throttled by it's own clock divider, leaving it's bus speeds intact.
300mhz DDRII is blazingly fast for DOS-era stuff. The cross-flashed BIOS I got had a hidden option "DDRII power saving". I don't know what exactly it does, but it cuts the bandwidth of the RAM by about 25%
Planet's Edge is now playable, but barely (still a bit fast). Looks like i'll need to solder another strap to lower the DDR clock, but I'm reluctant to do so yet.
I'm afraid it will cripple the system to the point that I will be unable to achieve a comfortable performance in Nascar Racing.
So, summing this up:
Would someone be interested in developing a tool or adding support to existing one to control this cpu's registers in term of clock control and L1-I\L1-D\\L2 caches?
I'm willing to make any test necessary on my part.
Hardware strap info, benchmarks and other data will be poster and updated here:
https://docs.google.com/spreadsheets/d/1wEa2x … dit?usp=sharing