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16 bit ethernet card in 8 bit ISA

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First post, by GabrielKnight123

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Can a 16 bit ethernet card be used in an 8 bit ISA bus or will this slow it down, it's for a Toshiba T3200SX

Reply 1 of 24, by Sphere478

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I’ve typically gotten 1mb/sec out of 10 base and 10mb/sec out of 100 base.

There were some 10/100 cards made for 16bit isa.

I’m getting mixed info from google on how fast 8 and 16 bit isa was.

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Reply 2 of 24, by GabrielKnight123

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I have several 16 bit cards I think they are all 10 base but I'm selling and helping someone with a T3200SX and he only has 8 bit ports but if my cards are 10 base I guess in an 8 bit slot they will be 500kb/sec

Reply 6 of 24, by Grzyb

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Yes, 3C509B is known to work in 8-bit slot, but:
- must be set to IRQ that's present on 8-bit ISA, ie. IRQ 7 or lower
- special packet driver may be necessary, but I'm not sure, it's possible it's only required for PC/XT

Would it be slower than in 16-bit slot?
Maybe... but I wouldn't worry, 386SX-16 probably isn't fast enough to fully use 10 Mbps anyway...

Reply 7 of 24, by Disruptor

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Yes, it is possible.
For NE2000 cards you may need drivers that are aware that such a card is in an 8 bit slot. (Not too few drivers / setup programs have a bug in this used case!)

Reply 8 of 24, by mkarcher

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Disruptor wrote on 2022-01-05, 13:31:

For NE2000 cards you may need drivers that are aware that such a card is in an 8 bit slot. (Not too few drivers / setup programs have a bug in this used case!)

In fact, I wouldn't call it a bug. It's just an unsupported configuation for standard NE2000 drivers. For MTCP, see https://www.vcfed.org/forum/forum/genres/pcs- … for-8-bit-slots for a patched driver to support NE2000 (compatible) cards in 8-bit slots.

Reply 9 of 24, by GabrielKnight123

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Alright, I'll look up the manual for a card that might be called an ELEC5 E333OB with a SMC UltraChip but before I do has anyone had this card working in an 8 bit bus

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Reply 10 of 24, by BitWrangler

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Grzyb wrote on 2022-01-05, 12:56:

Maybe... but I wouldn't worry, 386SX-16 probably isn't fast enough to fully use 10 Mbps anyway...

The CPU and RAM should handle 100Mbit even, but HDD in that age of machine is likely to tap out at 5Mbit, if not less.

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Reply 11 of 24, by weldum

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i have a ne2000 based card (genius kye) and it works perfectly on my Cyrix MediaGX machine, it only has 1 8bit isa slot for expansion
the board needed a fixed irq but the standard windows generic ne2000 driver picks it up normally
about performance... it may be lower than the 10mbit limit, i don't have a way to verify correctly the speed under windows 95

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Reply 12 of 24, by Grzyb

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BitWrangler wrote on 2022-01-05, 14:42:
Grzyb wrote on 2022-01-05, 12:56:

Maybe... but I wouldn't worry, 386SX-16 probably isn't fast enough to fully use 10 Mbps anyway...

The CPU and RAM should handle 100Mbit even, but HDD in that age of machine is likely to tap out at 5Mbit, if not less.

100 Mbps = 12.5 MB/s
386SX-16 means 16-bit bus * 16 MHz = 32 MB/s

In theory looks good, in practice... NO WAY.

I've done extensive bechmarking of 100 Mbps Ethernet on 386DX-40, and the best it could do was around 900 KB/s.
Well, using TCP/IP - I guess it could be better with some lighter protocol.
But there's still the limit of ISA bus, therefore impossible to approach 100 Mbps.

Reply 13 of 24, by Deksor

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Grzyb wrote on 2022-01-05, 16:49:
100 Mbps = 12.5 MB/s 386SX-16 means 16-bit bus * 16 MHz = 32 MB/s […]
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BitWrangler wrote on 2022-01-05, 14:42:
Grzyb wrote on 2022-01-05, 12:56:

Maybe... but I wouldn't worry, 386SX-16 probably isn't fast enough to fully use 10 Mbps anyway...

The CPU and RAM should handle 100Mbit even, but HDD in that age of machine is likely to tap out at 5Mbit, if not less.

100 Mbps = 12.5 MB/s
386SX-16 means 16-bit bus * 16 MHz = 32 MB/s

In theory looks good, in practice... NO WAY.

I've done extensive bechmarking of 100 Mbps Ethernet on 386DX-40, and the best it could do was around 900 KB/s.
Well, using TCP/IP - I guess it could be better with some lighter protocol.
But there's still the limit of ISA bus, therefore impossible to approach 100 Mbps.

Yes but ISA isn't clocked at the same speed as the main CPU. It sits somewhere around 8MHz most of the time. So in reality the entire bandwdith is ~16MB/s (without counting waitstates, interrupts, activity of other cards and whatever that makes the bus much slower)

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Reply 14 of 24, by mkarcher

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Deksor wrote on 2022-01-05, 16:53:

Yes but ISA isn't clocked at the same speed as the main CPU. It sits somewhere around 8MHz most of the time. So in reality the entire bandwdith is ~16MB/s (without counting waitstates, interrupts, activity of other cards and whatever that makes the bus much slower)

The fastest ISA cycles are zero-waitstate 16-bit memory cycles. They already take two ISA clocks to complete, so the theoretical limit of (non-overclocked) ISA is 8MB/s. Because writes can be pipelined, practival performance can actually approach 8MB/s in CPU-to-memory writes. ET4000 cards are prominent examples that usually max out the ISA interface on 16-bit writes. Depending on the mainboard, actual performance (of burst 16-bit writes) is between 5MB/s and 7MB/s.

Most ISA network cards do not use shared memory (because configuring shared memory in upper memory space is inconvenient to inexperienced users) or busmastering (because ISA bus mastering is a pain to get working correctly with most mainboards, and gets problematic as soon as you have more than 16MB RAM). So they rely on I/O cycles for data transfer. Depending on who you ask, 2-clock I/O cycles on the ISA are

  • not allowed by the specification
  • impossible due to broken specifications ("require a negative propagation delay")
  • underspecified, by work in practice

I am with the first camp. I consider the specification not to be broken in itself. In no place it mandates a negative propagation delay ("/0WS needs to be asserted before address lines are guaranteed to be stable"). You only get to that conclusion if you start at the (IMHO wrong) assumption that 2-cycle I/O writes should be possible. Instead, if you dump that assumption and just accept the fact that the fastest possible I/O cycles require three clocks, it's perfectly possible to conform to all ISA timing requirements, and use the /0WS signal to overide extra wait states possibly generated by the chipset. At 3 clocks per 16 bits transferred, the theoretical maximum data rate is 5.6MB/s. This theoretical rate could be closely matched (at 100% CPU usage just for sending frames to the network card) for transmits, but is unlikely to be reached on reception, because you can't pipeline I/O reads. An I/O read starts with the CPU requesting some data, and the frontside bus is blocked until the data arrives. Any delay between the start of the CPU cycle and the start of the ISA cycle and any delay in forwarding data from ISA to the CPU add to the 3 ISA clock minimum time of I/O reads.

Reply 15 of 24, by BitWrangler

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Yes, 16bit ISA at 8Mhz is too slow, 8bit ISA at 4.77Mhz or 8Mhz is slower, but the claim was the CPU is too slow, and it is that I disputed. Sure if you really wanna run 100Mbit on a 386 you'd wanna look at MCA or EISA.

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Reply 16 of 24, by Deksor

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mkarcher wrote on 2022-01-05, 17:26:
The fastest ISA cycles are zero-waitstate 16-bit memory cycles. They already take two ISA clocks to complete, so the theoretical […]
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Deksor wrote on 2022-01-05, 16:53:

Yes but ISA isn't clocked at the same speed as the main CPU. It sits somewhere around 8MHz most of the time. So in reality the entire bandwdith is ~16MB/s (without counting waitstates, interrupts, activity of other cards and whatever that makes the bus much slower)

The fastest ISA cycles are zero-waitstate 16-bit memory cycles. They already take two ISA clocks to complete, so the theoretical limit of (non-overclocked) ISA is 8MB/s. Because writes can be pipelined, practival performance can actually approach 8MB/s in CPU-to-memory writes. ET4000 cards are prominent examples that usually max out the ISA interface on 16-bit writes. Depending on the mainboard, actual performance (of burst 16-bit writes) is between 5MB/s and 7MB/s.

Most ISA network cards do not use shared memory (because configuring shared memory in upper memory space is inconvenient to inexperienced users) or busmastering (because ISA bus mastering is a pain to get working correctly with most mainboards, and gets problematic as soon as you have more than 16MB RAM). So they rely on I/O cycles for data transfer. Depending on who you ask, 2-clock I/O cycles on the ISA are

  • not allowed by the specification
  • impossible due to broken specifications ("require a negative propagation delay")
  • underspecified, by work in practice

I am with the first camp. I consider the specification not to be broken in itself. In no place it mandates a negative propagation delay ("/0WS needs to be asserted before address lines are guaranteed to be stable"). You only get to that conclusion if you start at the (IMHO wrong) assumption that 2-cycle I/O writes should be possible. Instead, if you dump that assumption and just accept the fact that the fastest possible I/O cycles require three clocks, it's perfectly possible to conform to all ISA timing requirements, and use the /0WS signal to overide extra wait states possibly generated by the chipset. At 3 clocks per 16 bits transferred, the theoretical maximum data rate is 5.6MB/s. This theoretical rate could be closely matched (at 100% CPU usage just for sending frames to the network card) for transmits, but is unlikely to be reached on reception, because you can't pipeline I/O reads. An I/O read starts with the CPU requesting some data, and the frontside bus is blocked until the data arrives. Any delay between the start of the CPU cycle and the start of the ISA cycle and any delay in forwarding data from ISA to the CPU add to the 3 ISA clock minimum time of I/O reads.

Thanks for the full explanation !

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Reply 17 of 24, by mkarcher

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Grzyb wrote on 2022-01-05, 16:49:

100 Mbps = 12.5 MB/s
386SX-16 means 16-bit bus * 16 MHz = 32 MB/s

The 386 (SX or DX) front-side bus needs two clocks for a transfer in the best case (a pipelined zero-waitstate cycle). That means a 386SX-16 has a theoretical limit of 16MB/s, and a 386DX-40 has a theoretical limit of 80MB/s. As soon as you copy from the shared memory of a network card to main memory, copying alone pushes each word over the bus twice, so the theoretical limit goes down to 8MB/s for the SX case you mentioned. And this doesn't even include the time needed to process the data...

For 100MBit, you would definitely want something faster than a 386SX-16, or a smart network card with offloading features for the protocol used. Just for fun: try estimating the theoretical maximum rate for TCP/IP checksum calculation on a 386SX-16.

Reply 19 of 24, by PC Hoarder Patrol

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The actual chip (83C790) seems to have been a partial clone of the WD8003 / 8013, though the SMC archive doesn't have anything specific on the chip or any of the cards that used it; only its direct replacement, the 83C795 which had backwards compatibility to the 83c790 and its drivers

https://web.archive.org/web/19970715140826/ht … eets/83c795.pdf