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First post, by Baoran

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I am building socket 7 system. CPU is K6-III+ and currently set to 5.5 x 66Mhz. Motherboard is SY-5EMA+ that has MVP3 chipset, 1024KB of L3 cache and there is currently 2x256MB ram sticks installed.
I have been trying to find out clear information on effect of cacheable ram but I have found some conflicting information.
Is it that if I remove one of the ram sticks the performance should improve because all ram would be cacheable or is it because of the L2 cache on the cpu that there should be no change performance?
Like I read about 8bit tag in MVP3 chipset and it being limited to 256MB cacheable ram, but then there is also that L2 cache on the cpu mixing things.

Reply 1 of 14, by Disruptor

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Since your L3 cache on MVP3 is write back you need 2048KB of L3 SRAM to cover your 512 MB of DRAM.
Surely the L2 cache on your CPU die will cover full 4 GB, but the performance drop because of the reduced cacheable area of your L3 can be measured and will cost some fps.

Reply 4 of 14, by dionb

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Baoran wrote on 2022-04-24, 19:21:
I am building socket 7 system. CPU is K6-III+ and currently set to 5.5 x 66Mhz. Motherboard is SY-5EMA+ that has MVP3 chipset, 1 […]
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I am building socket 7 system. CPU is K6-III+ and currently set to 5.5 x 66Mhz. Motherboard is SY-5EMA+ that has MVP3 chipset, 1024KB of L3 cache and there is currently 2x256MB ram sticks installed.
I have been trying to find out clear information on effect of cacheable ram but I have found some conflicting information.
Is it that if I remove one of the ram sticks the performance should improve because all ram would be cacheable or is it because of the L2 cache on the cpu that there should be no change performance?
Like I read about 8bit tag in MVP3 chipset and it being limited to 256MB cacheable ram, but then there is also that L2 cache on the cpu mixing things.

Basically the sources are both right:

- staying inside cachable limit will maximize performance because all memory can be cached by motherboard cache.
- on a K6plus with on-die L2 cache, the impact of L3 cache on the motherboard is so small as to be considered negligible.

If you're running benchmarks and care about absolute highest score to last decimal, get thet RAM back inside cachable limits. If not, you're not going to notice anything either way.

Just to complicate matters, consider that in everyday use the biggest bottleneck on a system (by far) is storage performance, and if you use all that extra RAM to do a lot of disk caching, the benefit of that will far exceed the tiny difference in raw memory performance.

Another factor is operating system. Win9x in particular is dumb and tends to load its most used bits into uncached RAM. There's a patch for that though, see here: http://www.redline.ru/~ipl/win2cache_eng.htm

So, bottom line: probably won't matter noticeably with a CPU with its own cache controller able to cache everything. However it's also true that this much RAM is pretty nonsensical on a system like this, unless you're doing something very specific, so probably you're best off dropping to 256MB or less.

Reply 5 of 14, by Sphere478

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The cpu supports 6x if you set it to 2x.

Mvp3 supports 100mhz minimum usually.

And most k6-3+ cpus will do 600mhz

I’m running 640mb of ram on my 3+ and mvp3 and I can play halo. 🤷‍♂️ I got 2048k of 4ns L3

I could do a test where I shed some ram and see what happens maybe. I think 384 is a little faster in some things but not a whole lot

Sphere's PCB projects.
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Sphere’s socket 5/7 cpu collection.
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SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
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Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 6 of 14, by Repo Man11

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Asus TXP4 with 256 megs of RAM installed and a K6-3+ @ 500 MHz enabling the motherboard's cache noticeably lowers memory bandwidth as measured by Sandra;

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"I'd rather be rich than stupid" - Jack Handey

Reply 7 of 14, by Sphere478

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Repo Man11 wrote on 2022-04-24, 22:32:

Asus TXP4 with 256 megs of RAM installed and a K6-3+ @ 500 MHz enabling the motherboard's cache noticeably lowers memory bandwidth as measured by Sandra;

I noticed that on my 430tx but on ss7 it seems to be the other way around. Not sure if it’s the chipsets or just the higher fsb. Suspect mainly the higher fsb.

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 8 of 14, by Repo Man11

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My Soyo SY-5EMA+ with a K6-3 450 and 256 megabytes of RAM (two 128 sticks) compared with 512 (the 128s and a 256), all else the same.

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"I'd rather be rich than stupid" - Jack Handey

Reply 9 of 14, by Sphere478

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Repo Man11 wrote on 2022-04-25, 01:17:

My Soyo SY-5EMA+ with a K6-3 450 and 256 megabytes of RAM (two 128 sticks) compared with 512 (the 128s and a 256), all else the same.

It’s not fair!!! 😂🤣 we want speeeeeed and ramz!!!

Sphere's PCB projects.
-
Sphere’s socket 5/7 cpu collection.
-
SUCCESSFUL K6-2+ to K6-3+ Full Cache Enable Mod
-
Tyan S1564S to S1564D single to dual processor conversion (also s1563 and s1562)

Reply 10 of 14, by Baoran

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Thank you for the info
I originally put the both sticks in the system because it was a kit of identical modules from bit newer broken duron system so I thought it would be better to keep them together.

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In this test it did change the memory numbers quite a bit after I just removed one of the memory modules. It feels bit strange though since it shouldn't actually speed up the L1 and L2 cache, right?

Reply 11 of 14, by Baoran

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I was also just running Sandra and I came to a conclusion that there has to be some kind of myth about that cacheable ram that I dont know about. The amount of Sisoft Sandra memory score drops when I add second 256MB stick is exactly the same amount no matter if I have external cache disabled in bios or not. Anyone has any ideas about this?

Reply 13 of 14, by H3nrik V!

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But, doesn't cacheable range depend more on tag ram than actual amount of cache? Surely, the more cache, the more data can be stored there, but again, isn't the tag responsible for indexing cache contents, and thus the main dependency for cacheable range?
Pentium II was available in a version that could cache 512 MiB and one that could cache 2GiB, same 512 KiB cache, but different tag ram ...

Please use the "quote" option if asking questions to what I write - it will really up the chances of me noticing 😀

Reply 14 of 14, by pentiumspeed

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No. What cacheable range means is specific design of the cache controller in specific chipsets with external tag ram(s) and cache size all these many varible determines the cacheable range same thing with CPU built in L2 cache on other end. K6-III plus can cache rest of the cache with motherboard's external cache disabled, IIRC. Not stacked on each other, since the extneral cache becomes L3 and overrides the processor's L2 in cacheable range if I think correctly.

Cheers,

Great Northern aka Canada.