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First post, by Baoran

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On SY-5EMA+ motherboard and K6-3+ cpu when testing with speedsys things are normal with single 256MB memory stick and speedsys shows 3 levels of cache in the graph but if you add second 256MB stick the reading test stays the same but writing test becomes flat like all 3 levels of cache would be disabled when writing to memory.

I dont really need 2 sticks there but if anyone knows why this happens just for writing and even with the cache that is on the cpu I would like to know.

Reply 2 of 23, by Baoran

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majestyk wrote on 2022-05-10, 05:58:

What size is the onboard L2 cache?
Are the two SDRAM sticks you tried the same size and what size?
Is there an option in the BIOS to enable/disable memory interleave?

2 identical 256MB PC133 sticks. Originally taken from a duron system.
There is no option for memory interleave in bios.

Reply 3 of 23, by majestyk

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Just a guess: As far as i remember the VIA MVP(3) chipsets needed 2MB of L2 cache to cache 512MB RAM. This is probably also the case when L2 cache acts as L3 cache under a K6+ CPU. In case there´s only 512K or 1MB L2 cache on your board (you didnt tell us so far) - depending on the Soyo BIOS, L2 cache might get disabled when there´s not enough L2 cache present.
For further investigation you could try with 2x128MB RAM...

Reply 4 of 23, by Baoran

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majestyk wrote on 2022-05-10, 08:57:

Just a guess: As far as i remember the VIA MVP(3) chipsets needed 2MB of L2 cache to cache 512MB RAM. This is probably also the case when L2 cache acts as L3 cache under a K6+ CPU. In case there´s only 512K or 1MB L2 cache on your board (you didnt tell us so far) - depending on the Soyo BIOS, L2 cache might get disabled when there´s not enough L2 cache present.
For further investigation you could try with 2x128MB RAM...

Well, I already knew MVP3 cant cache full 512MB because of the limitation of chipset, but still it does not really explain why all L1, L2 and L3 gets disabled and just for writing to ram while still working when it comes to reading in speedsys.

Reply 5 of 23, by Baoran

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Here is the speedsys picture with all writing related lines at the bottom of the graph.

socket7-a.jpg
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Here is the same with one of the sticks removed.

socket7-b.jpg
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Reply 6 of 23, by Gmlb256

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Baoran wrote on 2022-05-10, 17:26:
majestyk wrote on 2022-05-10, 08:57:

Just a guess: As far as i remember the VIA MVP(3) chipsets needed 2MB of L2 cache to cache 512MB RAM. This is probably also the case when L2 cache acts as L3 cache under a K6+ CPU. In case there´s only 512K or 1MB L2 cache on your board (you didnt tell us so far) - depending on the Soyo BIOS, L2 cache might get disabled when there´s not enough L2 cache present.
For further investigation you could try with 2x128MB RAM...

Well, I already knew MVP3 cant cache full 512MB because of the limitation of chipset, but still it does not really explain why all L1, L2 and L3 gets disabled and just for writing to ram while still working when it comes to reading in speedsys.

They don't get disabled, all three are unable to cache more than their maximum size and each data written by SpeedSys is fully randomized AFAIK.

Reply 7 of 23, by Baoran

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Gmlb256 wrote on 2022-05-10, 17:35:
Baoran wrote on 2022-05-10, 17:26:
majestyk wrote on 2022-05-10, 08:57:

Just a guess: As far as i remember the VIA MVP(3) chipsets needed 2MB of L2 cache to cache 512MB RAM. This is probably also the case when L2 cache acts as L3 cache under a K6+ CPU. In case there´s only 512K or 1MB L2 cache on your board (you didnt tell us so far) - depending on the Soyo BIOS, L2 cache might get disabled when there´s not enough L2 cache present.
For further investigation you could try with 2x128MB RAM...

Well, I already knew MVP3 cant cache full 512MB because of the limitation of chipset, but still it does not really explain why all L1, L2 and L3 gets disabled and just for writing to ram while still working when it comes to reading in speedsys.

They don't get disabled, all three are unable to cache more than their maximum size and each data written by SpeedSys is fully randomized AFAIK.

But cpu internal cache isn't suppose to have such limitation as motherboard cache has about how much ram can be cached or am I wrong about that?

Reply 8 of 23, by majestyk

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Even if L1 could still work fine, BIOS can do whatever it likes here. Maybe it´s a BIOS bug? You could try earlier/later versions if any exist or try a BIOS from a different board with the same chipset and super-io. Look out for MVP3 based mainboards with SMC super-io like the DFI K6XV3+ (without "66").

Reply 10 of 23, by Gmlb256

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Baoran wrote on 2022-05-11, 10:01:
Gmlb256 wrote on 2022-05-10, 17:35:
Baoran wrote on 2022-05-10, 17:26:

Well, I already knew MVP3 cant cache full 512MB because of the limitation of chipset, but still it does not really explain why all L1, L2 and L3 gets disabled and just for writing to ram while still working when it comes to reading in speedsys.

They don't get disabled, all three are unable to cache more than their maximum size and each data written by SpeedSys is fully randomized AFAIK.

But cpu internal cache isn't suppose to have such limitation as motherboard cache has about how much ram can be cached or am I wrong about that?

Didn't notice how both "Writing" and "MMX Writing" was a flat line with 512MB RAM until now tbh. 😜

And yes, the CPU internal cache is independent of the motherboard chipset limitations. Those flat lines aren't normal when the amount of RAM is above the cacheable limit.

Reply 11 of 23, by Baoran

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Gmlb256 wrote on 2022-05-11, 13:51:
Baoran wrote on 2022-05-11, 10:01:
Gmlb256 wrote on 2022-05-10, 17:35:

They don't get disabled, all three are unable to cache more than their maximum size and each data written by SpeedSys is fully randomized AFAIK.

But cpu internal cache isn't suppose to have such limitation as motherboard cache has about how much ram can be cached or am I wrong about that?

Didn't notice how both "Writing" and "MMX Writing" was a flat line with 512MB RAM until now tbh. 😜

And yes, the CPU internal cache is independent of the motherboard chipset limitations. Those flat lines aren't normal when the amount of RAM is above the cacheable limit.

Yeah. That is what this whole thread was about if anyone has any idea why it happens. I think it is the reason why I also get lower results in other memory benchmarks with 512MB, so I am curious what is causing it.

Reply 13 of 23, by Baoran

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majestyk wrote on 2022-05-11, 17:29:

L1 cache may be independant of chipset limitations but its not independant of BIOS decisions. BIOS can disable it anytime for whatever reason be it intentional or due to a bug.

Can it disable it just for writing and not reading? It seems to be just standard award bios.

Reply 14 of 23, by Gmlb256

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majestyk wrote on 2022-05-11, 17:29:

L1 cache may be independant of chipset limitations but its not independant of BIOS decisions. BIOS can disable it anytime for whatever reason be it intentional or due to a bug.

True, the CPU internal cache is likely set to write-through by the BIOS. Similar to rasz_pl mentioned above.

Baoran wrote on 2022-05-11, 17:50:

Can it disable it just for writing and not reading? It seems to be just standard award bios.

Could you check with CHKCPU to see what information says about the internal cache on that motherboard?

Reply 15 of 23, by Repo Man11

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It's the same with my Epox MVP3G-M.

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"Everyone is ignorant, only on different subjects." - Will Rogers

Reply 16 of 23, by Baoran

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Gmlb256 wrote on 2022-05-11, 18:44:
True, the CPU internal cache is likely set to write-through by the BIOS. Similar to rasz_pl mentioned above. […]
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majestyk wrote on 2022-05-11, 17:29:

L1 cache may be independant of chipset limitations but its not independant of BIOS decisions. BIOS can disable it anytime for whatever reason be it intentional or due to a bug.

True, the CPU internal cache is likely set to write-through by the BIOS. Similar to rasz_pl mentioned above.

Baoran wrote on 2022-05-11, 17:50:

Can it disable it just for writing and not reading? It seems to be just standard award bios.

Could you check with CHKCPU to see what information says about the internal cache on that motherboard?

CHKCPU says that L1 cache is enabled in write-back mode with both 256MB and 512MB.

Reply 17 of 23, by Gmlb256

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Baoran wrote on 2022-05-12, 03:41:
Gmlb256 wrote on 2022-05-11, 18:44:
True, the CPU internal cache is likely set to write-through by the BIOS. Similar to rasz_pl mentioned above. […]
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majestyk wrote on 2022-05-11, 17:29:

L1 cache may be independant of chipset limitations but its not independant of BIOS decisions. BIOS can disable it anytime for whatever reason be it intentional or due to a bug.

True, the CPU internal cache is likely set to write-through by the BIOS. Similar to rasz_pl mentioned above.

Baoran wrote on 2022-05-11, 17:50:

Can it disable it just for writing and not reading? It seems to be just standard award bios.

Could you check with CHKCPU to see what information says about the internal cache on that motherboard?

CHKCPU says that L1 cache is enabled in write-back mode with both 256MB and 512MB.

So rasz_pl and I were wrong about the assumption that it was being set write-through with 512MB. 😐

Reply 18 of 23, by Baoran

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Gmlb256 wrote on 2022-05-12, 05:13:
Baoran wrote on 2022-05-12, 03:41:
Gmlb256 wrote on 2022-05-11, 18:44:

True, the CPU internal cache is likely set to write-through by the BIOS. Similar to rasz_pl mentioned above.

Could you check with CHKCPU to see what information says about the internal cache on that motherboard?

CHKCPU says that L1 cache is enabled in write-back mode with both 256MB and 512MB.

So rasz_pl and I were wrong about the assumption that it was being set write-through with 512MB. 😐

Or chkcpu info is wrong. I also tried all memory related settings in bios and none of them affect if writing to memory having cpu cache disabled. Only thing that seems to affect it is if there is 512MB or 256MB of ram.

Reply 19 of 23, by Baoran

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I did another test and 256MB does not seem to be the absolute limit. I did put 3 128MB sticks of ram on the motherboard for total of 384MB and caches were working as they should be.

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