Please share some photos of the area, which was affected by the battery leakage. Have you checked what's going on under each IC? Some traces could be broken under them, which is not visible without full desoldering

Ask and you shall receive.

This was how the board came to me:

I proceeded to remove the socket:

I then cleaned it and diagnosed the traces:

I then fixed the broken traces I found with bodge wirse under the board and added a new socket:

This is the test result, hangs at 05 (Initializing KBC):

RESET line on KBC is 5V (High) which I think should have gone Low at boot, it never does.

appiah4 wrote on 2023-02-01, 07:32:

RESET line on KBC is 5V (High) which I think should have gone Low at boot, it never does.

PWR_GOOD is supposed to be tied to mobo reset, to make sure it is initialized properly only after the PSU provides stable voltages. Original PC design used KBC (since it's a separate MCU with its own timed reset and/or brownout detector) to process PWR_GOOD into system reset, or at least have it connected to tell the difference between power-on event (also HW reset) and SW reset. On newer boards this can be done entirely in the chipset but before Pentium this depends on the mobo.

First, see if pressing reset button (connect one) helps any on powered system. As I said it depends on the mobo so even if it doesn't do anything you should look into PWR_GOOD signal some more. I see you repaired the connection between PSU connector and nearby via, but what about the rest of the trace that goes down to the KBC, and further still? No breaks there?

If PWR_GOOD seems OK then the issue might be KBC not getting a correct clock signal. Mobo can't tell if KBC is still in reset or just dead and not responding, so code will be the same.

Deunan wrote on 2023-02-01, 12:42:

PWR_GOOD is supposed to be tied to mobo reset, to make sure it is initialized properly only after the PSU provides stable voltag […]
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appiah4 wrote on 2023-02-01, 07:32:

RESET line on KBC is 5V (High) which I think should have gone Low at boot, it never does.

PWR_GOOD is supposed to be tied to mobo reset, to make sure it is initialized properly only after the PSU provides stable voltages. Original PC design used KBC (since it's a separate MCU with its own timed reset and/or brownout detector) to process PWR_GOOD into system reset, or at least have it connected to tell the difference between power-on event (also HW reset) and SW reset. On newer boards this can be done entirely in the chipset but before Pentium this depends on the mobo.

First, see if pressing reset button (connect one) helps any on powered system. As I said it depends on the mobo so even if it doesn't do anything you should look into PWR_GOOD signal some more. I see you repaired the connection between PSU connector and nearby via, but what about the rest of the trace that goes down to the KBC, and further still? No breaks there?

If PWR_GOOD seems OK then the issue might be KBC not getting a correct clock signal. Mobo can't tell if KBC is still in reset or just dead and not responding, so code will be the same.

As far as I can remember the remaining trace is fine but I will recheck.

As for the KBCLK signal, I can't seem to find where it is supposed to come from. The board has two oscillators, Y1 and Y2, one of which is the default PCI clock. I THINK some logic chip somewhere is supposed to generate the KBCLK for this circuit, but I can't really tell which trace I need to check for continuity.. I will look deeped into this.

I did not try resetting the powered on system, interesting call. I will do this.

Even on 286 mobos KBC clock is not a local crystal but comes from the chipset, often via a 74 buffer to boost it. There might be a need for 2 clocks on some KBC chips, anti-phase to each other, so the signal will pass through some negating gate for the second input. In fact that 74F04 you have there under the KBC socket is a good candidate for being the amp/negation (though F is kinda a waste, LS would work too, but possibly it also has other functions). Can't see the markings on the other small DIP.

Do note it might be a connection between the gates in the 74F04 that's a problem, not between '04 and KBC itself. Desolder those two chips as well if in doubt. Preferably test the presence of clock with a scope (pins 2 & 3 of KBC, IIRC) but if you don't have a scope then a decent voltmeter (with at least 1Meg+ input impedance) should show voltage at about 2.5V (roughly half of 5V Vcc since clock should be 50% duty cycle). That voltage is not 100% guarantee the clock is there but pretty good indicator. In that case the search gets much bigger since with clock present you'd expect either the control lines (A0, /RD, /WR and /CS) or data (D0-D7) to be busted. That too can be found but is much more work.

Pin 4 of the keyboard controller ("/RESET") is an active low reset signal. It may be high all the time, as it is active low. You might have trouble seeing a power-on reset on that signal when it's low for just 50ms after power on, but that would be fine. Pin 21 (CPU RESET, "P20") is an output signal that is again meant to be high all the time unless the CPU instructs the KBC to output a low pulse on that pin. So I don't think you have to worry about RESET for now.

If the CPU can't interface with the KBC, your issue might be on the low data bits D0 and D1 (they are used as "KBC ready" signals, pins 12 & 13), or on the /CS pin (pin 6), on the /RD or /WR pins (pin 8 and pin 10), or on the register select pin (pin 9). In a typical AT system, /RD is connected to ISA /IOR, /WR is connected to ISA /IOW, D0 and D1 may be connected to the ISA bus, but might also be on a different bus segment that is decoupled by driver chips. Usually, D0 and D1 of the keyboard controller is directly connected with D0 and D1 of the BIOS chip even if the ISA data pins and the KBC data pins are not connected. /CS is generated by the chipset on most 486 boards when address 60 or 64 is accessed. Some 486 chipsets use a combined chip select signal for the keyboard controller (responds only to I/O cycles) and the BIOS ROM (responds only to memory cycles). The register select pin is pin 2 of the I/O address, and should be connected to A2 on the ISA bus and/or A2 on the BIOS ROM chip.

Checking for a KBC clock (as Deunan suggested) is also a good idea. The KBC won't work unless a proper clock signal is present at pin 2. This signal can be generated from a central clock generator or using the internal oscillator driver of the KBC by connecting a crystal between pins 2 and 3. When the keyboard controller receives a valid clock on pin 2, it will output a clock signal on pin 3. Probing directly at pin 3 is a good way to check for a clock at the KBC without being afraid of loading the oscillator down so it stops oscillating.

Verifying the connections I enumerated is a good idea to find broken traces/joints around the keyboard controller.

mkarcher wrote on 2023-02-01, 18:56:

Pin 4 of the keyboard controller ("/RESET") is an active low reset signal. It may be high all the time, as it is active low. You […]
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Pin 4 of the keyboard controller ("/RESET") is an active low reset signal. It may be high all the time, as it is active low. You might have trouble seeing a power-on reset on that signal when it's low for just 50ms after power on, but that would be fine. Pin 21 (CPU RESET, "P20") is an output signal that is again meant to be high all the time unless the CPU instructs the KBC to output a low pulse on that pin. So I don't think you have to worry about RESET for now.

If the CPU can't interface with the KBC, your issue might be on the low data bits D0 and D1 (they are used as "KBC ready" signals, pins 12 & 13), or on the /CS pin (pin 6), on the /RD or /WR pins (pin 8 and pin 10), or on the register select pin (pin 9). In a typical AT system, /RD is connected to ISA /IOR, /WR is connected to ISA /IOW, D0 and D1 may be connected to the ISA bus, but might also be on a different bus segment that is decoupled by driver chips. Usually, D0 and D1 of the keyboard controller is directly connected with D0 and D1 of the BIOS chip even if the ISA data pins and the KBC data pins are not connected. /CS is generated by the chipset on most 486 boards when address 60 or 64 is accessed. Some 486 chipsets use a combined chip select signal for the keyboard controller (responds only to I/O cycles) and the BIOS ROM (responds only to memory cycles). The register select pin is pin 2 of the I/O address, and should be connected to A2 on the ISA bus and/or A2 on the BIOS ROM chip.

Checking for a KBC clock (as Deunan suggested) is also a good idea. The KBC won't work unless a proper clock signal is present at pin 2. This signal can be generated from a central clock generator or using the internal oscillator driver of the KBC by connecting a crystal between pins 2 and 3. When the keyboard controller receives a valid clock on pin 2, it will output a clock signal on pin 3. Probing directly at pin 3 is a good way to check for a clock at the KBC without being afraid of loading the oscillator down so it stops oscillating.

Verifying the connections I enumerated is a good idea to find broken traces/joints around the keyboard controller.

Coming back to this board after a long break, some checks and findings:

KBC D0 and D1 are connected to BIOS EPROM D0 and D1
KBC D0 and D1 are NOT directly connected to ISA BUS D0 and D1 (Measure 1450 Ohms)
KBC /RD is connected to ISA /IOR
KBC /WR is NOT connected to ISA /IOW (Measures 1820 Ohms)
KBC /CS is connected to BIOS A2
KBC /CS is NOT connected to ISAA2 (Measures 1450 Ohms)

KBC Pin 2 is SHORT to GROUND - I believe this is where the problem is, where it expects a clock signal, it gets GROUND!

I think I may have a theory..

The top IC inside the KBC is a DM706N Hex Inverting Buffer. Pin 13 (A6) of that IC is connected to Pin 37 (KBCLK) of the KBC. Pin 12 (Y6) of the Hex Inverter has a damaged trace though. If you look at the photo with the KBC socket removed, it runs alongside Pins 4-3 of the KBC before disappearing.

I assumed that it was connected to Pin 1 of the KBC (Red Line). Which made sense at the time, as Pin 1 is T0 and functions as K/B Clock Input.

However, that pin is also connected to the Keyboard port and I think that it should get its K/B Clock signal from the Keyboard itself!

After all, KBCLK signal from Pin 37 is actually an output not an input! As a result, I think it was meant to travel through the Hex inverter and get routed to Pin 2 of the KBC, ie XIN (Blue Line).

I'll test that theory tomorrow. In the meantime, I'd be happy if someone would comment on how stupid my reasoning is 🤣

appiah4 wrote on 2023-06-12, 21:06:

KBC D0 and D1 are connected to BIOS EPROM D0 and D1 KBC D0 and D1 are NOT directly connected to ISA BUS D0 and D1 (Measure 1450 […]
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KBC D0 and D1 are connected to BIOS EPROM D0 and D1
KBC D0 and D1 are NOT directly connected to ISA BUS D0 and D1 (Measure 1450 Ohms)
KBC /RD is connected to ISA /IOR
KBC /WR is NOT connected to ISA /IOW (Measures 1820 Ohms)

It's surprising that /RD and /WR is handled differently. This might be a problem.

appiah4 wrote on 2023-06-12, 21:06:

KBC /CS is connected to BIOS A2
KBC /CS is NOT connected to ISAA2 (Measures 1450 Ohms)

This is surprising. The pin connected to A2 should be pin 10, called A0 (possibly some sources call it "RS" for "register select", I think I remember that name, too). A2 should not be connected to pin 6 (/CS).

appiah4 wrote on 2023-06-12, 21:06:

KBC Pin 2 is SHORT to GROUND - I believe this is where the problem is, where it expects a clock signal, it gets GROUND!

No, the 8042 does not expect a clock signal on pin 2. It expects a clock signal on pin 3. Pin 2 is an output pin that excites a crystal oscillator connected between pins 2 and 3 to produce a clock input on pin 3. If there is no dedicated crystal, but the keyboard clock is generated by the chipset, it's usual to not care about pin 2. I've seen working boards that ground this pin, and likely that's not a problem because a pin meant to excite a crystal oscillator likely already have a quite high output impedance, so shorting them to ground doesn't cause damage - nevertheless, I pesonally don't like seeing that pin grounded. I don't think pin 2 being grounded is the cause of your issue.

appiah4 wrote on 2023-06-12, 22:08:

I think I may have a theory.. […]
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I think I may have a theory..

The top IC inside the KBC is a DM706N Hex Inverting Buffer. Pin 13 (A6) of that IC is connected to Pin 37 (KBCLK) of the KBC. Pin 12 (Y6) of the Hex Inverter has a damaged trace though. If you look at the photo with the KBC socket removed, it runs alongside Pins 4-3 of the KBC before disappearing.

I assumed that it was connected to Pin 1 of the KBC (Red Line). Which made sense at the time, as Pin 1 is T0 and functions as K/B Clock Input.

However, that pin is also connected to the Keyboard port and I think that it should get its K/B Clock signal from the Keyboard itself!

In the AT keyboard interface, both CLK and DATA are bidirectional signals that can be driven by either the keyboard or the keyboard controller. Both the mainboard and the keyboard have open-collector outputs (the 7406 is a high-voltage, high-current open collector inverter). The classic AT design uses pin 37 to control the 7406 to pull the keyboard clock line low on the PC side. It also uses pin 1 to read the current state of the keyboard clock line. The same is true for the data line. The keyboard controller reads the data line on pin 39, but it uses an inverter in the 7406 controlled by pin 38 to pull the clock line low if required.

appiah4 wrote on 2023-06-12, 22:08:

After all, KBCLK signal from Pin 37 is actually an output not an input! As a result, I think it was meant to travel through the Hex inverter and get routed to Pin 2 of the KBC, ie XIN (Blue Line).

No, that theory makes no sense. Having a processor generate a signal that directly controls the clock this very processor requires to operate is not a good idea, also, pin 2 is the output of the keyboard controller (i.e. input to the Crystal), and driving something to that pin is useless.

mkarcher wrote on 2023-06-12, 22:17:

It's surprising that /RD and /WR is handled differently. This might be a problem.

This will be the next thing I move on.

mkarcher wrote on 2023-06-12, 22:17:

This is surprising. The pin connected to A2 should be pin 10, called A0 (possibly some sources call it "RS" for "register select", I think I remember that name, too). A2 should not be connected to pin 6 (/CS).

This is my bad. It is connected to BIOS A0 indeed. This checks out.

mkarcher wrote on 2023-06-12, 22:17:

No, the 8042 does not expect a clock signal on pin 2. It expects a clock signal on pin 3. Pin 2 is an output pin that excites a crystal oscillator connected between pins 2 and 3 to produce a clock input on pin 3. If there is no dedicated crystal, but the keyboard clock is generated by the chipset, it's usual to not care about pin 2. I've seen working boards that ground this pin, and likely that's not a problem because a pin meant to excite a crystal oscillator likely already have a quite high output impedance, so shorting them to ground doesn't cause damage - nevertheless, I pesonally don't like seeing that pin grounded. I don't think pin 2 being grounded is the cause of your issue.

OK, so Pin 2 being grounded is kind of OK, that means the KBC should be coming from the Chipset.

mkarcher wrote on 2023-06-12, 22:25:

In the AT keyboard interface, both CLK and DATA are bidirectional signals that can be driven by either the keyboard or the keyboard controller. Both the mainboard and the keyboard have open-collector outputs (the 7406 is a high-voltage, high-current open collector inverter). The classic AT design uses pin 37 to control the 7406 to pull the keyboard clock line low on the PC side. It also uses pin 1 to read the current state of the keyboard clock line. The same is true for the data line. The keyboard controller reads the data line on pin 39, but it uses an inverter in the 7406 controlled by pin 38 to pull the clock line low if required.

OK, so that seems to make sense then, that the KBCLK signal coming from the AT keyboard as well as the Pin 37 of the KBC to be connected to Pin 1 of the KBC.

mkarcher wrote on 2023-06-12, 22:25:

No, that theory makes no sense. Having a processor generate a signal that directly controls the clock this very processor requires to operate is not a good idea, also, pin 2 is the output of the keyboard controller (i.e. input to the Crystal), and driving something to that pin is useless.

I got super excited thinking I had it, but now that I read your explanation I must have come across as super dumb. 😅

At least this means my initial bodge wiring decision was correct..

So how do you propose I go from here? I guess checking into /WR is the first order of business. I'll try to map out where it connects to and how.

I guess I also need to make sure that the KBC is getting a KBCLK from the chipset. Not sure how I can do that though. I could try to find the Chipset datasheet and figure out the pin that sends out KBCLK, and try to verify continuity. But more than that, I'm at a loss. I'm understanding that this signal should be connected to KBC's Pin 3 (TAL2).. Would it be possible to see whether Pin 3 has anything going out with just a multimeter? I do not have an oscilloscope or a logic probe I'm afraid 🙁

Hello appiah4, logic probe is the next step I suppose.
It's quite simple to use and some stuffs can be fixed with this unexpensive tool. Just don't shake during contact testing 😀
I once used it to locate and repair a cutted pin track, that was difficult to see visually.

appiah4 wrote on 2023-06-13, 07:06:

OK, so Pin 2 being grounded is kind of OK, that means the KBC should be coming from the Chipset.

I suppose you mean "keyboard controller clock" when you write KBC here. Make sure to not mix up the "keyboard clock" (pin 1/37), which only ticks during data transfer at around 20kHz and the processor clock for the keyboard controller (pin 3), which oftentimes is 7.16MHz (OSC / 2).

appiah4 wrote on 2023-06-13, 07:06:

OK, so that seems to make sense then, that the KBCLK signal coming from the AT keyboard as well as the Pin 37 of the KBC to be connected to Pin 1 of the KBC.

Indeed. That's the standard AT keyboard keyboard controller wiring.

appiah4 wrote on 2023-06-13, 07:06:

So how do you propose I go from here? I guess checking into /WR is the first order of business. I'll try to map out where it connects to and how.

Yeah, that's definitely a good idea.

appiah4 wrote on 2023-06-13, 07:06:

I guess I also need to make sure that the KBC is getting a KBCLK from the chipset. Not sure how I can do that though. I could try to find the Chipset datasheet and figure out the pin that sends out KBCLK, and try to verify continuity. But more than that, I'm at a loss. I'm understanding that this signal should be connected to KBC's Pin 3 (TAL2).. Would it be possible to see whether Pin 3 has anything going out with just a multimeter? I do not have an oscilloscope or a logic probe I'm afraid 🙁

It's not super reliable, but just checking the voltage at pin 3 using a multimeter can give some hints. The clock needs to be high some times, and low at other times. In TTL logic, "high" is typically around 3.5 to 4.0 Volts, and "low" is around 0.2 to 0.4 Volts. A valid clock signal thus shold measure around 1.6 to 2.0 volts for TTL levels, or around 2.5 volts for CMOS levels, which is definitely between "clearly low" and "cleary high". If I read 1.5 to 2.2 Volts on a clock line, I expect it to be OK for a first assesment.

appiah4 wrote on 2023-06-12, 22:08:

I think I may have a theory..

Perhaps this piece of schematic will help you. As for pin 2 being grounded, it's unusual. It should be used or left unconnected. Some designs provide external clock to both pins 2 and 3, except anti-phase (ie the signal to one of the pins must go through inverting gate). Is that a dead short or something that looks like a battery spill resistance? You can always try inserting the KBC chip into a socket with pin 2 bent away a bit so that it doesn't make contact.

mkarcher wrote on 2023-06-14, 22:40:

I suppose you mean "keyboard controller clock" when you write KBC here. Make sure to not mix up the "keyboard clock" (pin 1/37), which only ticks during data transfer at around 20kHz and the processor clock for the keyboard controller (pin 3), which oftentimes is 7.16MHz (OSC / 2).

Indeedi I meant KB_CLK sorry 🙁

mkarcher wrote on 2023-06-14, 22:40:

It's not super reliable, but just checking the voltage at pin 3 using a multimeter can give some hints. The clock needs to be high some times, and low at other times. In TTL logic, "high" is typically around 3.5 to 4.0 Volts, and "low" is around 0.2 to 0.4 Volts. A valid clock signal thus shold measure around 1.6 to 2.0 volts for TTL levels, or around 2.5 volts for CMOS levels, which is definitely between "clearly low" and "cleary high". If I read 1.5 to 2.2 Volts on a clock line, I expect it to be OK for a first assesment.

For Pin 3, with the KBC installed I get a 1.98-1.99V reading. Curiously, I get I measure 1.83V at the socket with no KBC installed. Is that normal, I wonder?

Deunan wrote on 2023-06-14, 23:07:

Perhaps this piece of schematic will help you. As for pin 2 being grounded, it's unusual. It should be used or left unconnected. Some designs provide external clock to both pins 2 and 3, except anti-phase (ie the signal to one of the pins must go through inverting gate). Is that a dead short or something that looks like a battery spill resistance? You can always try inserting the KBC chip into a socket with pin 2 bent away a bit so that it doesn't make contact.

I inserted the KBC with Pin 2 bent out and it made no difference. There are no traces leading from Pin 2 on either side of the board. It looks like it connects directly to the ground plane, somehow.

A question, should I be able to measurethe battery voltage on any pin of the KBC or BIOS EPROM or anyone else on the board for that matter when there is no mains power? Because I can't, even with the external battery (3V CR2035) connected.. Going by @Deunan 's schematic I should read the battery voltage at Pin 26 of the KBC (VDD) right? I get 4.88V with mains connected, 0V with it unplugged. Maybe it's not booting up because the battery circuit (battery damage was worst there) is an issue?

Great Success!

The board's 4 pin external battery connector was configured as OCCO with the barrel battery so I always assumed the external battery connection would be +OO-.

Wrong!

I checked the lanes from VDCC and PROG on the KBC and figured it was actually O+O- and when I connected it this way.

Also, the 72-pin SIMM slots were labeled SIMM8 & SIMM7, so I assumed SIMM7 (below) was Bank 0.

Wrong!

I had to move the SIMM to SIMM7 for the board to POST:

Two last issues remain:

1. The board is VERY picky about both 72-pin and 30-pin RAM. Even with RAM it POSTs with it detects and test up toonly 1MB for some reason.
2. Keyboard not present or keyboard error on POST. However the keyboard (a PS2 connected using a PS2 to AT adapter) works fine, I can open and save the bios..

Any ideas?

KBC shouldn't need battery voltage at all. RTC does but on this mobo RTC/NVRAM should be part of the chipset. Though I do spy a small barrel crystal that's probably a 32kHz for the RTC, and the DIP nearby should be low-power CMOS inverter like 4069. That chip should have battery power on it's VCC pin - through a diode, so that it can be powered by +5V from PSU while the system is running.

In general missing battery voltage should not prevent the system from booting unless there is some jumper that needs to be set, without which there is no power (at all, even with PSU) to some parts of the chipset like the RTC domain for example.

As for your RAM troubles - some 486 mobos are super picky about RAM chips, escpecially the 72-pin ones. See if installing 36-bit (partity) sticks helps. The keyboard error is puzzling if it actually works, perhaps the KBC isn't reset properly?

Another interesting problem: Cache is always detected as 1024KB (regardless of what I set via jumpers) and never works, so the system is always about as fast as a 286-20 🙁