Or sync cache up to 1MB using Intel COAST version 1.0 but I could not find the PDF for designing the COAST version 1.0, anyone could help here?

There are many data sheets on COAST modules from their manufacturers, but none of them described a 1Mb version. Make a high res scan of your module to see what can be done about it.

Why did this board have soldered U30 tag ram even the COAST module already have tag ram included even this board does have COAST slot already.

It's for 32Kx1 SRAM used as dirty bits to double cacheable range. SiS5511 supports up to 1Gb of memory, but not that much cacheable. It can do 128Mb with 1Mb write back cache using 32Kx8 tag configured as 7+1 bits or 256Mb with 1Mb write through cache using all 8 bits. Additional 32Kx1 boosts the range to 256Mb in write back mode.

ph4nt0m wrote on 2023-02-03, 04:02:

There are many data sheets on COAST modules from their manufacturers, but none of them described a 1Mb version. Make a high res […]
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Or sync cache up to 1MB using Intel COAST version 1.0 but I could not find the PDF for designing the COAST version 1.0, anyone could help here?

There are many data sheets on COAST modules from their manufacturers, but none of them described a 1Mb version. Make a high res scan of your module to see what can be done about it.

Why did this board have soldered U30 tag ram even the COAST module already have tag ram included even this board does have COAST slot already.

It's for 32Kx1 SRAM used as dirty bits to double cacheable range. SiS5511 supports up to 1Gb of memory, but not that much cacheable. It can do 128Mb with 1Mb write back cache using 32Kx8 tag configured as 7+1 bits or 256Mb with 1Mb write through cache using all 8 bits. Additional 32Kx1 boosts the range to 256Mb in write back mode.

Thank you so much for explanation, not very clear from the SiS 5511 datasheet.

What about the 512K pipelined burst cache using two tag rams then, the COAST with the one tag ram and motherboard's soldered tag ram?

Cheers,

pentiumspeed wrote on 2023-02-03, 23:05:

What about the 512K pipelined burst cache using two tag rams then, the COAST with the one tag ram and motherboard's soldered tag ram?

The second tag is never used for all 8 bits, just 1 to 3 bits. Many chipsets are limited to a single tag. It's a bit unclear how a particular manufacturer implemented tag access especially in weird scenarios with two tags soldered on board and two tags on the COAST. I usually check their PCB layout with a continuity tester to find out what can be done about it. Tag address lines are multiplexed with CPU and north bridge address lines while data lines are connected to the north bridge only. Since most north bridges of the COAST age are quad flatpacks, the tester helps there, too.

I need to make such 1Mb COAST for an unnamed Zeos mainboard which is very much like Boa 2

except it's based upon a newer VLSI Wildcat DP chipset (VL82C594 System Controller + 2x VL82C595 Data Buffers + VL82C597 PCI to ISA Bridge DP). It's pin compatible with VLSI SuperCore 590 (VL82C591 System Controller + 2x VL82C592 Data Buffers + VL82C593 PCI to ISA Bridge) of the Boa 2. I know for sure Wildcat DP supports 1Mb of cache, though it's unclear whether they implemented write back mode or not. SuperCore 590 does write through only.