Disruptor wrote on 2023-04-03, 06:15:Ah, it's a DX4 backport then. Then I do not wonder why it runs with 50 MHz FSB at all.
Perhaps it was binned down to DX2-66 beca […]
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Rav wrote on 2023-04-03, 06:12:
The complete model I have is the TI486DX2-G66-GA. It is 3.45v so maybe there is hope, going to do more research tomorrow...
Ah, it's a DX4 backport then. Then I do not wonder why it runs with 50 MHz FSB at all.
Perhaps it was binned down to DX2-66 because some tests at 100 MHz have failed (1st candidate is L1 cache ofc.).
Perhaps you have success with 3.6 Volt or 4.0 Volt.
And, yes, you may try first whether you get your L2 cache working in write back mode at 66 MHz.
Cyrix 486 had write back L1 even in their DX, while Intel has introduced it in the later DX4 first.
So you may need to try both jumper settings.
Tools:
the cache graphs in SpeedSys 4.78
ctcm 1.7a from c't (heise): ctcm7 /nop
I did notice that I get WT for L1 if the bus is 33, and WB if the bus is 40 or 50.
For the L2, it's WB for 33 and 40, then it's non existent for 50
Changing the CPU voltage won't change a thing for the L2 I think. It was already at 3.8 (oups). I set it back down to 3.45.
66Mhz(33fsb):
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