feipoa wrote on 2023-04-11, 00:05:

Thanks! I briefly looked at the config file. The most interesting options to try on my system would be the AT clock speed, which is stuck at 7.1 MHz, and the VL device ready sync mode, which is stuck on Sync mode. Bypass mode should be faster. Are you finished with the config file, or do you think there are more options to reveal?

The config file is not finished yet, I do plan to add more when I get more infos.
Also please note that the AT clock is the only setting that I'm not sure about. From my tests, I think the AT Clock is upside down (lower bit number = higher divider)

I have a VLB motherboard with this chipset. It performs quite ok as long as You are running a 33mhz fsb. As per the photo it supports 5v cpus only out of the box but I modded it to support lower voltage
cpu's. I tried a TI 486 DX2-80 but as has been reported it's slower than a dx2-66. I tried all the tricks with the jumpers but made no difference.
I'm quite happy to do dome tests and see if I can help with this.

There are a whole load of bios to try here https://theretroweb.com/motherboards/?showIma … 1&chipsetId=172
Some have Award, others Phoenix, and also AMI bios is used.

Rav wrote on 2023-04-11, 00:56:

feipoa wrote on 2023-04-11, 00:05:

Thanks! I briefly looked at the config file. The most interesting options to try on my system would be the AT clock speed, which is stuck at 7.1 MHz, and the VL device ready sync mode, which is stuck on Sync mode. Bypass mode should be faster. Are you finished with the config file, or do you think there are more options to reveal?

The config file is not finished yet, I do plan to add more when I get more infos.
Also please note that the AT clock is the only setting that I'm not sure about. From my tests, I think the AT Clock is upside down (lower bit number = higher divider)

I checked your ISA bus clock values using an oscilloscope. They are all correct as stated in the config file. On my system, I have CLK2 at 66.6 Mhz, so xxxxx011 = CLK2/6 = 11.11 MHz. Measured 11.1 Mhz on the scope. I checked all other values as well. The reserved value, 111, returns the same as 7.19 MHz.

My test used VLB graphics, so the increase in DOOM performance noted with adjusting the ISA clock values only comes into play with ISA sound enabled. With 7.19 MHz, it would scored 3101 realtics, for example, but at 13.3 MHz, it would return 3018 realtics.

Aside from DRAM/SRAM/Cache settings, none of the other options improved my memory read/write speeds or benchmark scores. If you are using ISA graphics, you should get improvements with LDEVJ, and ISA wait states options.

The VL Device Ready Syn mode, set to bypass - it would let me run DOOM, but upon exit, where it would normally show the benchmark result, my system would hang. Also, I got a hang in Landmark. I know I had issues with this on the S3 968 graphics card on other systems as well. Bypass, or Transparent mode, only works well with some graphics cards - I think the ATI Mach 64 was one of them.

feipoa wrote on 2023-04-13, 12:09:

I checked your ISA bus clock values using an oscilloscope. They are all correct as stated in the config file. On my system, I have CLK2 at 66.6 Mhz, so xxxxx011 = CLK2/6 = 11.11 MHz. Measured 11.1 Mhz on the scope. I checked all other values as well. The reserved value, 111, returns the same as 7.19 MHz.

Thanks for checking. I suspect my confusion come for some extra divider that come into play when I switch the board to 40MHz bus. I need to find a board (or someone with one) that does not halve the performance of the memory when switched to 40Mhz (to check the bios and/or dump the registers at 33 and 40mhz)

feipoa wrote on 2023-04-13, 12:09:

The VL Device Ready Syn mode, set to bypass - it would let me run DOOM, but upon exit, where it would normally show the benchmark result, my system would hang. Also, I got a hang in Landmark. I know I had issues with this on the S3 968 graphics card on other systems as well. Bypass, or Transparent mode, only works well with some graphics cards - I think the ATI Mach 64 was one of them.

Mine is set to Bypass by default. I have an onboard Cirrus Logic GD5430. It's a PCI card wired on the VLB bus. Performance is subpar on landmarks when bus is at 33/40 (midway between a ISA card and a VLB card, ~7300C/s). When the bus is set to 50Mhz, the card performance increase to ~9300C/s).

So there is many thing that get adjusted between 33 and 40 on my AG1X/2 board
* Videocard performance stay the same while I think it should go up
* Memory performance halve
* AT clock move in wrong direction (increasing bus would require a bigger at clock divider so it hit it's normal clock plus or less, while on my board I get a small divider)

Rav wrote on 2023-04-13, 15:21:

I have an onboard Cirrus Logic GD5430. It's a PCI card wired on the VLB bus.

The Cirrus Logic GD5430 is also found on some VL graphics cards like the Diamond Speedstar SE VLB.
So I don't think you have any PCI logic at all on your board, but some deactivated lurking in that graphics chip.

Disruptor wrote on 2023-04-13, 15:46:

Rav wrote on 2023-04-13, 15:21:

I have an onboard Cirrus Logic GD5430. It's a PCI card wired on the VLB bus.

The Cirrus Logic GD5430 is also found on some VL graphics cards like the Diamond Speedstar SE VLB.
So I don't think you have any PCI logic at all on your board, but some deactivated lurking in that graphics chip.

yes, GD5430 has dual bus support, nothing special about it
Btw I dont know why, but it took me years to realize Landmarks stupid text video speed test in "chr/ms" is nothing more than copy speed in KB/s. Would be nice to disassemble this part and see how un/optimized that routine is, like is it verbatim 8bit or 16 bit transfers.

Too bad about the funny business on your board at 40 MHz. Did you determine a proper combination of settings to get the ISA at 10 MHz when FSB=40 MHz?

You mentioned that you get L1:WB if bus is 40 or 50 MHz. Did chkcpu agree with this finding?

My board has two hidden settings for L1, namely,

Int. cache WB/WT Feature - WB/WT
Int. cache below 16M WB/WT - WB/WT

It is defaulted to WT, but I can use AMISETUP to adjust them to WB and save to CMOS RAM. However, when I installed an Am5x86 via a 486HPi Transcomputer module, chkcpu still showed L1 in write-thru mode. How many different CPUs did you check L1:WB functionality in?

feipoa wrote on 2023-04-14, 10:44:

Too bad about the funny business on your board at 40 MHz. Did you determine a proper combination of settings to get the ISA at 10 MHz when FSB=40 MHz?

You mentioned that you get L1:WB if bus is 40 or 50 MHz. Did chkcpu agree with this finding?

Yes, Internal (L1) cache : Enabled in Write-Back mode

Yes for ISA : Also I found for my AT clock weirdness, my board probably set the CLK2 to CLK when setting to 40 (so by setting 40fsb, CLK2 would be 40 instead of the expected 80).
While I don't have a scope, I did benchmark using my 3COM network card, I got the proper upload/download speed back after setting the AT clock to CLK2/4 (Assuming CLK2 is 40Mhz, that would make it 10Mhz).

By default, it's /8 for 33Mhz (8.25Mhz effective) bus and /6 for 40Mhz bus (6.66Mhz effective).

At least, that correlate with the performance of my ISA network card, so /4 (10Mhz) it is.

feipoa wrote on 2023-04-14, 10:44:

My board has two hidden settings for L1, namely, […]
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My board has two hidden settings for L1, namely,

Int. cache WB/WT Feature - WB/WT
Int. cache below 16M WB/WT - WB/WT

It is defaulted to WT, but I can use AMISETUP to adjust them to WB and save to CMOS RAM. However, when I installed an Am5x86 via a 486HPi Transcomputer module, chkcpu still showed L1 in write-thru mode. How many different CPUs did you check L1:WB functionality in?

I have only one CPU (For now) Looking for a DX4 from Intel or AMD.

I been looking to edit AMI bios to extract the setup table. I finally learned how to do that on AWARD but it seam that most of these ALI board have AMI bios.

Are you willing to dump registers for me? If I can't extract the setup table to get the registers, Then the is the other slow way to get the registers.

I attached my ALI1429 register dump program.
If you have time, you can set both settings to WT.

then you run the program like that : 1429dump > wtwt.txt

Then you change Int. cache WB/WT Feature to WB
1429dump > wbwt.txt

Then you change Int. cache WB/WT Feature back to WT and set Int. cache below 16M WB/WT to WB
1429dump > wtwb.txt

EDIT : Forget about that, I think these use CPU internal register, I found some informations about my Cyrix chip. (and there is a config file for ctchip34)
For Internal cache control, for my Cyrix, I have to unlock NW flag in CR0 register (Index C2h, bit 2)

Then I have to

mov eax,cr0
then using "and" command to mess with eax bits (NW = bit29 (0 = WT, 1 = WB), CD = bit30 (0 = L1 off, 1 = L1 on))
mov cr0,eax

Then I have to re-lock NW flag in CR0 register (Index C2h, bit 2)

OK, so no need the BIOS dump?

That is a lot of extra steps to get your Cyrix into WB mode. Did you try the Cyrix 5x86 utilities to see if their WB-enabling software works on your Cyrix DX4? Is it fully functional in WB mode on this board?

I should try a Cyrix DX4 on my board via the Transcomptuer to see if WB works. I think the WB-supporting Intel DX2 & DX4 and the AMD DX4/X5 used the WB/WT# pin to set WB/WT mode; Cyrixes were different. For unsupporting BIOSes, they usually shipped with software to do for you what you are describing with the NW bit.

However, I'd have suspected that my board's BIOS would have let my Am5x86 work in WB mode with the WB BIOS settings. On the Am5x86 Evergreen interposer, I have the WB jumper set. Maybe some function on the Transcomptuer interposer is causing a problem here.

On my ALi M1429 board, I've since had a fellow member unhide the VL Ready Sync/Bypass mode, the AT clock freq, and some BL3 and SXL2 clock doubling features. It will be interesting to see if your board can use some AMI BIOSes.

feipoa wrote on 2023-04-15, 07:12:

OK, so no need the BIOS dump?

Non, look like L1 cache operation is controlled from the CPU registers and are mostly documented.

feipoa wrote on 2023-04-15, 07:12:

That is a lot of extra steps to get your Cyrix into WB mode. Did you try the Cyrix 5x86 utilities to see if their WB-enabling software works on your Cyrix DX4? Is it fully functional in WB mode on this board?

It's a Cyrix DX2 I have, But it's operations (configuration registers) are the same as a DX4.
I never tried the 5x86 utilities, and I plan to make a small utility to control the L1 of all Cyrix 486 DX*

feipoa wrote on 2023-04-15, 07:12:

On my ALi M1429 board, I've since had a fellow member unhide the VL Ready Sync/Bypass mode, the AT clock freq, and some BL3 and SXL2 clock doubling features. It will be interesting to see if your board can use some AMI BIOSes.

I still have some issue to think for that BIOS upgrade. I plan to do it once I have a competent eeprom programmer But I'm not sure if I can do AMI. The thing is, to modify AMI bios, it seem that I need a specific version of amibcp from the old age that did not survive the time (no one have them). While there plenty of tools to modify Award BIOS.

I think I will have to modify the replacement BIOS because I need to have a Video rom for the onboard video. My board have an integrated VLB video card but no VLB port so I really want that video chip to continue to work.

Or maybe it's possible to stuff it into my 3COM card, if I can place it at the same location you think it could work? It seam to be located at C000-C7FF (32K). And it need to be initialized before all the other BIOS stuff (so I can go into setup after booting)

Rav wrote on 2023-04-16, 18:54:

feipoa wrote on 2023-04-15, 07:12:

OK, so no need the BIOS dump?

Non, look like L1 cache operation is controlled from the CPU registers and are mostly documented.

"It takes two to tango". In this case, a Cyrix 486 CPU needs to be configured to use L1 cache (in WT mode, in WB mode) using CPU registers. This is documented in the Cyrix BIOS writer's guide, which you can obtain. But at the same time, the mainboard chipset needs to interface with the Cyrix CPU in a Cyrix-specific way. The way how to program the chipset to use the Cyrix write-back protocol (and for power-management also: the way to get the Chipset to understand the Cyrix SMM protocol) depends on the chipset. Sometimes, the chipset is configured using jumpers, but most chipsets are configured by the BIOS, after the BIOS detected the CPU type. The knowledge how to set up the ALi 1529G to use the Cyrix WB and the Cyrix SMM protocol can only be found in ALi datasheets or from reverse engineering an ALi 1529G BIOS.

And as a final comment: Most (or all?) low-voltage Cyrix 486 processors do not use the Cyrix WB and Cyrix SMM protocol, but the Intel Enhanced DX2/DX4 ("&EW" / P24D) protocols. Those processors have "standard pinout" printed on them.