XTIDE supports fully configurable IO port addresses for the IDE controllers. Take a look at the documentation (https://www.xtideuniversalbios.org/), users *must* run the configuration tool to correctly configure a ROM image before writing it to an E(E)PROM, and that includes the ability to set the port addresses.

The defaults, when using the XT rom image are 0x300, and for AT images are 0x1F0/0x170/0x1E8/0x168. But the config menu allows the user to set any address they like.

See: Re: DIY 16-bit ISA IDE interface?
Primary is 1F0 (and IRQ 15), secondary is 170 (and IRQ 14), and there are also tertiary and quaternary ranges.
3F0 is the floppy port range not IDE. But, the "alternate status register" 3F6 is put smack in the middle of the floppy range.

If you use the standard ranges, it should work with any AT or higher BIOS, not just XTIDE Universal BIOS, but users might still want XTIDE BIOS for two reasons: 1. the 528MB limit and support for multi-sector per IRQ transfers, 2. some pre-1990 BIOSes have a race condition bug where they read a sector and acknowledge the IRQ from the drive in the wrong order, causing the BIOS to never receive the IRQ for the second sector.

The XT-IDE (8-bit) card uses a custom port range and IRQ that isn't IDE and you shouldn't anticipate trying to support both if that is what you were alluding to. That card needs logic to convert between 8-bit transfers (rep insb/rep outsb on a V20 or the non-string variants otherwise) and 16-bit transfers, while a 16-bit IDE card just passes 16-bit transfers (rep insw/rep outsw) directly to the drive. It also uses a different IRQ (<= 7) for obvious reasons. or doesn't use one at all.

It will just be a 16-bit controller. Not 8-bit stuff.
So I don't need for my purpose 300.
So 1F0 is for the primary IDE and and 170 is for the primary IDE as I understood jakethompson1.
From 1F0 to 1F7 are A0, A1 and A2 and the drive will be selected wenn the other address lines are showing 011110XXX. A0, A1 and A2 are going to all the IDE drives to A0 at pin 35, A1 at pin 33 and A2 at pin 36. But 1F and 17 only allows 2 drives in total, not 4. What also throws me of is that on some pinouts of the IDE port is that CS0 is sometimes refered 1F0/1Fx and CS1 as 3F6/3Fx. Or is my thinking wrong?
What also weird is that the controller from alexandrugroza.ro uses 376 and 3F6 to select drives on the IDE-buses.
(Sorry when I annoy, I unfortunately like to over complicate things)

Hi DocRaptor,

I am also doing work on a new mainboard design where I want to include the primary and secondary IDE ports.

Did you get any further with your work since this post?

I am trying to understand the situation of using these ports in a AT system.
There is some information I found but it's not clear and not conclusive.

I also found the information that port 1F0 controls CS0 and port 3F6 controls CS1.

So far it's clear however there is also the FDC_LDCR in a PC system which according to my previously used information listens to port 3F6, with the addition of A0 being controlled by the FDC itself. So it's also the question how the FDC listens to the ports, does it only listen to 3F7 where A0=1 or also tries to listen to 3F6? I have not gotten a clear answer to this up to now.

Using XT-IDE BIOS in an option ROM I have been succesful to control the primary AT IDE port on a 286. However this concerns a multi IO card and now I am going to create my own design which needs to include the FDC and IDE interfaces. So I am still researching how I am going to go about decoding this. Of course, it is possible since ATs were doing this already.

My theory at the moment is that it could possibly work to use 3F6 for the IDE and 3F7 for the FDC.
However the FDC may control by itself that it will respond to 3F6 when A0=0.

I also read some information in a FDC datasheet which may indicate that in "AT mode" the FDC may not need the FDC_LDCR register.
Maybe this was done to avoid these conflicts or for other reasons.
So possibly the conflicts may already be solved by existing BIOS software, which leads to another way.

Anyway, I will continue my research and may do some testing on a multi IO card in case I can't find anything conclusive.
Please let me know if you have found some information about this matter, and if you are still interested in this.

Kind regards,

Rodney

In case anyone is interested and arrives at this post through a search, I am posting the information as I am currently assuming to be correct and which I will be using myself.
No guarantees here and builder is at their own responsibility and risk for anything they do with this information.

After doing some testing on a floppy/IDE ISA card, so not a multi IO chip version, I believe the decoding on a typical early AT is probably done as follows:

/IDE1_CS0 = 1F0 (decode from SA3 until SA9, so this includes a range)
/IDE1_CS1 = 3F6 (decode from SA1 until SA9, should be a single address only even though SA0 is left "open")

/FDC_LDOR = 3F2 (decode from SA0 until SA9)
/FDC_CS = 3F4 (decode from SA1 until SA9 so 3F5 is included for selecting/using this CS)
/FDC_LDCR = 3F7 (decode from SA0 until SA9, single address only)

Chip selects are all negative active as the signal names indicate as well.

I believe this configuration to function properly because I used this card in one of my PCs.
As mentioned before here, the 3Fx area is rather fully used, so I believe this is how they did it.

It's also worth noting in case anyone writes their own software or BIOS code to control the FDC controller, I read in the datasheet for the GM82C765 that it and probably the 37C65 as well can be configured to run in "PC AT Mode" which is a compatibility mode for AT PCs, which is initiated by writing to /FDC_LDOR right after a hardware reset. This mode changes something in the output controls to the floppy drive cable and also enables certain DMA support in order for the DMA controller to control floppy access instead of the Intel CPU.

Kind regards,

Rodney

I was looking into that a while back as well: Re: How does ISA MEMCS16# work?