Archon wrote on 2023-05-05, 13:33:

- tried to trace RESET signal over the board, done some measurements with the scope and it seems like it does not react to manual reset whatsoever;

Is reset permanently active or permanently inactive? The reset pin of the 286 processor is active if it is high, as is pin B02 ("RESETDRV") on the ISA bus. You should see a falling edge on RESET for the system to start operation. You don't see RDY, which is used to end a cycle. But do you see any activity on 286 S0 and S1, which will start a cycle? If the processor is in RESET, for example, there will be no activity on S0 and/or S1, and thus there will be no activity on RDY, too, even with the RDY logic fully functional.

If you see S0/S1, but no RDY, check the IOCHRDY signal. If that signal is pulled low permanently, there are infinite wait states on any (ISA) bus cycle.

mkarcher wrote on 2023-05-05, 18:07:

Archon wrote on 2023-05-05, 13:33:

- tried to trace RESET signal over the board, done some measurements with the scope and it seems like it does not react to manual reset whatsoever;

Is reset permanently active or permanently inactive? The reset pin of the 286 processor is active if it is high, as is pin B02 ("RESETDRV") on the ISA bus. You should see a falling edge on RESET for the system to start operation. You don't see RDY, which is used to end a cycle. But do you see any activity on 286 S0 and S1, which will start a cycle? If the processor is in RESET, for example, there will be no activity on S0 and/or S1, and thus there will be no activity on RDY, too, even with the RDY logic fully functional.

If you see S0/S1, but no RDY, check the IOCHRDY signal. If that signal is pulled low permanently, there are infinite wait states on any (ISA) bus cycle.

Thanks mkarcher, so here's what I've found. S0, S1 and RESET on the 286 are all high. Same for the IOCHRDY on ISA bus. All of them keeps having stable ~5V.
fyi I've soldered all caps back after making sure they're ok.

I should point out that CAP pin has -3.8V, which is weird imho (that's why I've checked the capacitor nearby). I've measured it with respect to the ground ofc.

Archon wrote on 2023-05-05, 18:56:

Thanks mkarcher, so here's what I've found. S0, S1 and RESET on the 286 are all high.

RESET high is the root cause of all the other symptoms you are observing. RESET high keeps the processor in RESET mode. The processor waits for RESET to go low before it starts to do anything. As long as the processor doesn't start any bus cycle, so the mainboard is correct in not responding to any bus cycle. Your diagnosis approach to look at PWRGOOD is good. RESET is often generated based on PWRGOOD. Some older boards distrust PWRGOOD and monitor the power supply voltages to generate RESET. Check all the voltages (including -5V and -12V). In case all voltages are good: Try to find where RESET is generated, and analyze that circuit.

Maybe my advice won't be sophisticated but it' worth to check temperature of key IC ie. by touching them with finger. If any of ICs is really hot than it can help to narrow the inspection area.

mkarcher wrote on 2023-05-05, 19:34:

RESET high is the root cause of all the other symptoms you are observing. RESET high keeps the processor in RESET mode. The processor waits for RESET to go low before it starts to do anything. As long as the processor doesn't start any bus cycle, so the mainboard is correct in not responding to any bus cycle. Your diagnosis approach to look at PWRGOOD is good. RESET is often generated based on PWRGOOD. Some older boards distrust PWRGOOD and monitor the power supply voltages to generate RESET. Check all the voltages (including -5V and -12V). In case all voltages are good: Try to find where RESET is generated, and analyze that circuit.

Ok, will do, but certainly not today, I'm a bit tired from struggling with this. Thanks, I'll let you know the progress later!

zami555 wrote on 2023-05-05, 19:46:

Maybe my advice won't be sophisticated but it' worth to check temperature of key IC ie. by touching them with finger. If any of ICs is really hot than it can help to narrow the inspection area.

It's hard to tell actually, because the bigger part of the logic ICs are getting just a little bit warm. CPU is the hotspot here, so when I start to measure stuff on the board I sometimes use a small heatsink from GPU's VRM. Maybe this is also a sign of something bad happening?

Archon wrote on 2023-05-05, 19:58:

It's hard to tell actually, because the bigger part of the logic ICs are getting just a little bit warm. CPU is the hotspot here, so when I start to measure stuff on the board I sometimes use a small heatsink from GPU's VRM. Maybe this is also a sign of something bad happening?

That sounds fine. An 80286 CPU without heatsink may get to 40 to 50°C (that's around 105 to 120°F, I estimate), that's no reason to worry about the CPU being the hot spot. Logic ICs getting slightly warm is also expected. zami555 is suggesting to for logic ICs getting really hot (even hotter than the CPU). If a logic IC gets that hot, either that IC is broken, or some of the output pins of that ICs are involved in a short circuit. If there is no logic IC getting that hot, that way of easily locating a suspect area did not help in your case, but the general advice is good, nevertheless.

So here's what I've found:
- all voltages from PS are fine, within +/-10% range (-12V was -12.6, a bit too low but still within the tolerance I think);
- PowerGood signal from the PS goes directly to the inverter, then to pin 13 of MC146818P. This is a CE pin and it's expected to be low in order to enable chip logic, and... it is low;
- CKOUT of the MC146818P is unused as far as I can tell. I have no idea if it is somewhat helpful here;
- no IC's or any bigger component gets hot except the CPU, which is propably in the range that mkarcher mentioned;

I wander in the dark...

Early 286 in ceramic packages can easily burn fingers (and those have small heatsinks too) so I would advise to be very careful when "probing" any chips in 286 system with a finger. If only because pulling your hand quickly from a hot spot might result in some random damage or skin cuts over sharp edges.

Anyway, POWER_GOOD going to the /CE of RTC chip (via a gate) is a pretty standard solution on these mobos. This is to prevent any accidental reads/writes to CMOS during periods with unstable power (power on/off events). This is has nothing to do with CPU reset though.

CPU is reset by the chipset, which might implement a fast control over A20 gate and software CPU reset (to exit protected mode). This is also implemented in the 8042 keyboard controller. Chances are the KBC is not running and the state of its outputs fools the chipset into thinking the software reset is active. At least that is what I would be checking. Make sure the KBC has a clock on pins 2 and 3 (some of these chips will work with clock on just one of these pins), it's usually external clock from the chipset, very rarely the KBC has its own crystal oscillator. Pin 4 is RESET for the KBC (this is input, from chipset), I can't remember but I think it's active low. Pin 21 might be the soft reset output, again assuming it's not done inside the chipset.

BTW I had a similar problem once, these 286 mobos are big and old, susceptible to via cracking. On mine RESET was not reaching ISA slots. Since you are testing it out of the case try different mobo positions (on the side, upside down, etc). If you have such a microcrack it can often come and go with the mobo flexing so it's worth to check it out. Also let the mobo sit for 15 min powered if it is not smoking anywhere - then try a power cycle. The extra heat it accumulates might also change something.

Deunan wrote on 2023-05-06, 21:28:

CPU is reset by the chipset, which might implement a fast control over A20 gate and software CPU reset (to exit protected mode). This is also implemented in the 8042 keyboard controller. Chances are the KBC is not running and the state of its outputs fools the chipset into thinking the software reset is active. At least that is what I would be checking. Make sure the KBC has a clock on pins 2 and 3 (some of these chips will work with clock on just one of these pins), it's usually external clock from the chipset, very rarely the KBC has its own crystal oscillator. Pin 4 is RESET for the KBC (this is input, from chipset), I can't remember but I think it's active low. Pin 21 might be the soft reset output, again assuming it's not done inside the chipset.

Good point with the different RESETs: There is the CPU reset, and there is the system reset. We know that CPU reset is permanently active, next step to check is whether system reset is also permanently active. Two positions to test system RESET is pin B02 on the ISA bus (active high) and pin 4 on the KBC (active low indeed). If system RESET is active, CPU RESET is likely caused by system RESET, and you need to find out why system reset is active. If system RESET is not active, checking whether the KBC is requesting CPU reset by pulling down pin 21 is the logical next step. This board uses discrete logic instead of a chipset to interface the 80286 processor, so I don't expect "fast A20 gate" to be implemented.

Thanks guys. B02 is likely to be high (3.57V). Pin 4 on the KBC is indeed low. Pin 2 and 3 both gets 6MHz from the clock. Looks like it's all about this system RESET. I'll trace the signal but do you have any suggestion where to search for it? What part of the board might be responsible for generating this system RESET? There's actually no single chipset, it's all spreaded up to tens of IC's. Should I start tracing the line for B02 on the ISA bus?

How would a reset be handled in 286, simple RC circuit? 555?

So here's another update. B02 on ISA bus connects to 74ALS244N (9 pin). The logic behind it shows, that for the high state it expects Q (19) to be low and A (11) to be high. Q is indeed low, but A has 2.03V which is pretty close to undefined state. I've traced the signal further and A pin on that IC connects directly with reset switch (and a few other ICs). Once I keep reset button pressed, voltage goes to ~4.5V. After release it goes back to ~2V. However output for B02 stays at the same level, which is ~3.5V - it does not react to the reset button (also Q input stays low for the entire time).

Archon wrote on 2023-05-07, 10:18:

So here's another update. B02 on ISA bus connects to 74ALS244N (9 pin). The logic behind it shows, that for the high state it expects Q (19) to be low and A (11) to be high. Q is indeed low, but A has 2.03V which is pretty close to undefined state. I've traced the signal further and A pin on that IC connects directly with reset switch (and a few other ICs). Once I keep reset button pressed, voltage goes to ~4.5V. After release it goes back to ~2V. However output for B02 stays at the same level, which is ~3.5V - it does not react to the reset button (also Q input stays low for the entire time).

The 244 is a buffer chip ("buffer" is a term used by digital electronics folks to mean "digital amplifier"). Indeed, Pin 9 is the output of one of the 8 amplifiers in this chip. It makes a lot of sense to use an amplifier chip here, because there is some onboard logic and up to 8 ISA cards connected to that pin, and standard logic chips might not be strong enough to drive this signal reliably. This makes sense. Calling pin 19 "Q" is a strange naming convention. Usually, "Q" is used for flip-flop and RAM data output pins. Pin 19 is the "amplifier enable" pin. If that pin is high, pin 9 would do nothing, neither drive the reset signal high nor low. As RESET is likely always driven by this 74ALS244 chip, pin 19 might be directly connected to GND. This makes a lot of sense. Conventional names for pin 19 are "G" ("gate") or "EN" ("enable"). Nevertheless, even with the unconventional name, you described the function of the chip correctly.

The level on pin 11 is your true issue. When you push the reset button, that level goes "really high". This is correct. A high level at this point is meant to cause a system reset. But when you release the reset button, and there is no other reason to cause a system reset, this pin should be clearly below 1V. The 2.03V you measured here is still interpreted as "high", and this causes the output to stay "high" as well all the time. So your next task is to find out what is connected to pin 11. Obviously, the reset button is pulling this pin high, likely via some resistor. But there also is some logic pulling this pin low if everything is fine for operation. This might be a (possibly open-collector, likely schmitt-trigger) inverter connected to the "power good" signal. This might be a comparator like the LM393 used as threshold detector for an R/C reset circuit. This might be an R/C-based monostable timing chip like 555 or the 74xx123 (with xx being LS, HCT, ALS), or it might be just a transistor with PWRGOOD (via a resistor) on its base signal, and reset on the collector, emitter grounded.

Archon wrote on 2023-05-07, 10:18:

I've traced the signal further and A pin on that IC connects directly with reset switch (and a few other ICs).

You sure about that direct connection? It's weird for RESET switch (in fact any switch) to drive the signal High, the usual way it's done is the switch connects to GND (therefore drives Low) and there is a pull-up resistor of some 4k7 to +5V to provide H if the switch is not pressed.

244 is a buffer with input voltage hysteresis (aka Schmitt trigger) but non-inverting so it would need H input for H output. However I would expect the switch to operate as I described above and there being an inverter gate to sort it out, plus it's also unusual for the RESET switch to directly affect ISA signal.

In general the master reset signal is POWER_GOOD. But the chipset might have it's own circuit - anything from a simple RC network to some internal counter - that is used to properly reset entire mobo, or just the CPU/NPU pair, depending on what kind of reset is required. I think you mentioned there being a gate and connection to /CE on the RTC from POWER_GOOD - make sure the /CE is indeed low in steady state after power on. Try to figure out what the RESET switch pins are connected to, if indeed it's driving H then one should be connected to 5V Vcc via resistor up to 1k. Since the chipset must also be able to drive this line there should be an OC gate like 7406 or '07 that is also connected to the input of the '244 chips. Perhaps this gate died and is no longer capable of driving the signal L.

You're correct, I wrongly named it Q, but once I zoomed PDF a little bit, it is clearly displayed as G. My mistake, sorry 😀

Thanks you so much guys! I'll follow your advices today evening.

@Deunan - you're right. I should wrote that A pin reacts to RESET switch instead of that it's connected directly. It is not and lot of the logic is happening in the middle.

So I've spent some time finding stuff connected to pin 11 of 74ALS244N, here's the list:
- 74ALS74AP - pin 5 (output) - this one was so hard to identify that I had to apply IPA and use microscope to read the ID, no idea if it is anyhow important to notice though;
- 16L8APC - (PAL chip by AMD) pin 11 (input);
- 16R8BPC - (PAL chip by AMD) pin 9 (input);
- 74ALS02N - pin 11 (input);
- two D8237AC-5 chips on pin 13 (input);
- two 74ALS04AP:
1. pin 5, then from pin 6 it goes to KBC's pin 4, which is RESET;
2. pin 11, then from pin 10 it goes to 7407P - pin 3. Pin 4, literally goes to tens of places all over the board;

Should the first one (output) be the suspect here? Should I trace its signal further?

Archon wrote on 2023-05-07, 20:43:

- 74ALS74AP - pin 5 (output) - this one was so hard to identify that I had to apply IPA and use microscope to read the ID, no idea if it is anyhow important to notice though;

Should the first one (output) be the suspect here? Should I trace its signal further?

Yes, that one might be interesting. That's a D-type flip-flop. Latching the reset signal doesn't make that much sense, so I guess they use the flip-flop to synchronize the reset signal with the processor clock. If that's the case, pin 3 ("CLK") should receive the processor clock input signal (2* the nominal processor clock). Pin 2 ("D") should receive the unsynchronized reset signal. Pins 1 and 4 are likely high all the time, as the asynchronouse set and reset function are not required when you use a D-Flip-Flop to synchronize a signal with the clock. Examining Pin 2 is likely worth a shot.

Maybe that chip is broken. It might be hard to read, because it got quite hot which decomposed some of the paint. Maybe it doesn't mean anything that the chip is hard to read. I suggest you check the other pins with a scope. Pin 2 is intended to go low a split second after power up, which will be forwarded to Pin 5 on the next clock cycle. Pin 3 is intended to receive a clock signal. Verify all of that.

Archon wrote on 2023-05-07, 20:43:

Should the first one (output) be the suspect here? Should I trace its signal further?

Please make sure the /CE pin on RTC does indeed go low when power is applied.

Then, assuming it is low, measure the state of pins 1,2,3 and 4 on that '74 flip-flop. It's a not a setup I'm familiar with so it can be a synchronizer or it might just be used as a dumb RS via the async inputs. So we have to know what is driving it first. Also do a quick test if the pin 2 is connected to pin 9, because a single stage synchronizer is not very good, a two stage (and we do have two FF in the '74) would be much better. If there is such connection you can then investigate the other half of the chip, but first please check all the pins I mentioned.