Likely TAG0 is used for the indication whether modified data is in the write-back L2 cache that needs to be written back to the RAM before it gets replaced by other data. This is called the "dirty" or "altered" bit. If the L2 cache operates in write-through mode, cache lines in the L2 cache are never dirty, so this RAM chip is not required. I'm afraid that boards like yours usually run L2 cache always in write-back mode, though, and a missing TAG0 chip will either result in a non-functional system (obviously, it doesn't in your case), or it will degrade performance, because the chipset has to assume that the L2 cache is always dirty, even if it is clean. This will cause extra write-back cycles that cause delays while the processor is stalled waiting for fresh data. Adding the missing chip will increase performance (probably around 5 to 15 percent, depending on the application).

EDIT: I checked the data sheet: The L1 can operate in write-through mode. This board in WT mode doesn't need the extra tag chip, and performs quite good. In most use cases, WB with the extra tag chip is better, but there are some cases in which WB with tag decreases performance compared to WT. It's still true that you want to avoid WB without that extra tag chip. If you BIOS offers the choice between write-through and write-back, do choose write-through unless/until you got the extra tag chip.

With your 64 kB of L2 cache, obviousely operating in write through mode, please do not install more than 16 MB of RAM.
Otherwise there will be an uncached area in your RAM with that small amount of cache.
Note that that dirty tag ram will be quite different from your other SRAM chips.

Yes that chip will most likely be a 64kx1 SRAM like a CY7C187-15PC but finding the exact one the board is wired for may be a bit tricky....

Jamieson wrote on 2023-05-07, 12:58:

I have the 486 motherboard "SIH 486B" from NIC Technology. It seems to be properly configured for 64kB cache with 8 x 8Kx8 cache chips installed, TAG1 is 8Kx8, but TAG0 is empty. According to the datasheet TAG0 should be 16Kx4 in all cache configurations.

According to the chipset datasheet, 16K x 4 is a waste at 64KB cache. You only need that size at 256K cache. At 64KB cache, a 4K x 4 chip will be enough, even a 4K x 1 chip would do - but the 4K x 4 chips likely and the 4K x 1 chip definitely will have a different pinout, so the mainboard manual is likely correct that the design of the mainboard requires a 16K x 4 chip at all cache sizes, although the chipset will only use 4K x 1 of it. The reason for using a x4 chip instead of an x1 chip is that the x4 chips were considerably more common at that time. If you have spare 4Kx1 chips and feel like investing (aka wasting) time on it, it is definitely possible to design an adapter to use it instead of the 16K x 4 chip the board is designed for.

Horun wrote on 2023-05-07, 15:59:

Yes that chip will most likely be a 64kx1 SRAM like a CY7C187-15PC but finding the exact one the board is wired for may be a bit tricky....

Nope, not with this board. While 64K x 1 is a common size for the dirty tag chip, this board uses 16K x 4, as seen in the manual scan in the OP. This is a carry-over from the time where the address tag was also stored in multiple x4 chips: At 256K cache, a very common early configuration was 8* 32K x 8 for the data, and 3* 16K x 4 for the tag (two chips for address tag, one chip for dirty tag). Not using a x1 chip simplified the bill of materials.

mkarcher wrote on 2023-05-07, 16:06:

Horun wrote on 2023-05-07, 15:59:

Yes that chip will most likely be a 64kx1 SRAM like a CY7C187-15PC but finding the exact one the board is wired for may be a bit tricky....

Nope, not with this board. While 64K x 1 is a common size for the dirty tag chip, this board uses 16K x 4, as seen in the manual scan in the OP. This is a carry-over from the time where the address tag was also stored in multiple x4 chips: At 256K cache, a very common early configuration was 8* 32K x 8 for the data, and 3* 16K x 4 for the tag (two chips for address tag, one chip for dirty tag). Not using a x1 chip simplified the bill of materials.

Thanks ! somehow I missed that, a bit unusual indeed ! Finding the exact one still be tricky, have to seek out the address lines and match up. Just looked at some diff 16kx4 and seems there are two diff sets of address numbered pins...

Horun wrote on 2023-05-07, 16:38:

Thanks ! somehow I missed that, a bit unusual indeed ! Finding the exact one still be tricky, have to seek out the address lines and match up. Just looked at some diff 16kx4 and seems there are two diff sets of address numbered pins...

It doesn't matter which address pin has which number, as long as the same pins are address pins, the chips are compatible. There is no kind of burst mode or page mode in which the order of memory cells is significant. There are two different pinouts, though: One includes /OE (output enable) and has 24 pins, and the other one does not include /OE and uses just 22 pins. I counted the socket on the board, and it has 22 pins, so the OE-less pinout variant is required. For Cypress, that means the CY7C164 is a match, the CY7C166 doesn't fit.

On a quick google research, I found the following 22-pin 16k x 4 SRAMs: MT5C6404, CY7C164, IDT7188, QS8888A. All of them have address pins on 1-9 and 17-21.

Thanks for the responses. I'll get this motherboard reinstalled in the case and check the BIOS setup again... it may offer the choice between write-through and write-back L2 cache modes.

mkarcher wrote on 2023-05-07, 20:52:

It doesn't matter which address pin has which number, as long as the same pins are address pins, the chips are compatible. There is no kind of burst mode or page mode in which the order of memory cells is significant. There are two different pinouts, though: One includes /OE (output enable) and has 24 pins, and the other one does not include /OE and uses just 22 pins. I counted the socket on the board, and it has 22 pins, so the OE-less pinout variant is required. For Cypress, that means the CY7C164 is a match, the CY7C166 doesn't fit.

On a quick google research, I found the following 22-pin 16k x 4 SRAMs: MT5C6404, CY7C164, IDT7188, QS8888A. All of them have address pins on 1-9 and 17-21.

OK thanks, never knew you could that under any circumstance. My brain just gained another wrinkle, and it hurt 🤣