Deunan wrote on 2023-07-21, 08:56:

... but the primary problem of these CPUs remain: the 386 bus protocol can't do burst cache line loads, so you only get speedups from code loops and frequently used data that is small enough not to spill. Which, even at 8k L1 (still 2-way at best), is difficult to achieve.

You have first world problems. 😀 I used to have a 486SLC2 in a laptop. It has the same limitation regardings bursts, it has half the bus width (386SX instead of 386DX bus protocol) and just 1KB L2 cache - yet they used a clock doubling processor to sell it as "50MHz 486 Laptop". I didn't fall for the marketing myself. I got it as a gift when it was fully obsolete[1] (and obviously never really used).

1: Well, it was already kind-of obsolete when it was produced, but I'm talking about 2000 here.