Sorry about the delay. I saw this post but haven’t had a moment to take proper photographs of the board. I snapped a few today.

I bought this board and so far, it seems pretty solid. I modified the BIOS using MODBIN to fix the dirty TAG—it’s sub-optimally configured such that the alter bit/TAG setup is permanently configured as 8+0 bits. The setting for 7+1 is there, but hidden, so I just un-hid it. My big issue with the alter bit setup is that the L2 is permanently set in WB mode and all settings pertinent to such are hidden; I likewise un-hid those, not that WT L2 is always desired, but the option is nice.

I believe this board to be a Chaintech 4SLE M104 a/k/a Mylex MGI486: https://theretroweb.com/motherboards/s/chaintech-4sle. There are M103, M105, and M106 silkscreened boards and some of them have different jumpers. Interestingly, this particular board is not correctly silkscreened for the P24D. To setup an Intel L1 WB-type CPU, you have to use the 486DX/SL configuration and add a separate jumper to the WB/WT pin, which is simple enough.

This particular board has the VRM, and I plan to remove one of the factory-soldered jumpers that sets 3.3v only operation and add a pin header to enable 3.3v and 4v operation. That’s a pretty sweet plus.

I found out that this is one of very few boards with proper support for the Cx486S+Cx487S combination, which makes it pretty useful. I don’t know if it supports the FasCache’s internal L1 Burst WB mode, but it supposedly does per the BIOS settings; however, I can’t see a difference in performance benchmarks when enabled/disabled. The only other boards that I personally can confirm as working with the Cx486S+Cx487S are the M912 (barely, as it’s not really stable), and the EXP4045 (which works great). The EXP4044 can handle the Cx486S but does not work with the Cx487S—nothing happens. Newer boards drop support for the M6 CPU and 487S FPU altogether. I suspect that, as the Cx486S is basically a Cx486DLC with 2kb of L1 cache, there’s some design considerations that were just altogether intentionally eschewed or unintentionally dropped on later boards.

Unfortunately, the board’s TAG is limited to DIP-28 parts, and that means the total cache size is limited to 512kb maximum. Do you or does anyone know if there’s a way to simply add a DIP-32 socket and wire up the extra 4 pins? One is Vcc, one is NC, and the other two are A15/A16, which I suspect would have to be wired directly to the chipset, and that seems simple enough given that the SiS471 datasheet is publicly available and Vcc is Vcc…

Let me know if you want more pics as well. I can also attach the original and modded BIOSes, if desired.

Hello,

Thank you for the response.

I dont know whats about this:

I bought this board and so far, it seems pretty solid. I modified the BIOS using MODBIN to fix the dirty TAG—it’s sub-optimally configured such that the alter bit/TAG setup is permanently configured as 8+0 bits. The setting for 7+1 is there, but hidden, so I just un-hid it. My big issue with the alter bit setup is that the L2 is permanently set in WB mode and all settings pertinent to such are hidden; I likewise un-hid those, not that WT L2 is always desired, but the option is nice.

I never looked after. What means 8+0 bits over 7+1. Does this mean the TAG isn`t configured to work? Iam guessing 8 are the cache ICs and 0 is the tag IC?

I cant make up whats written on you vrm.. On a guess i would say its an EZ1086ct?

If i want to chance that cash config. Its maybe better to use my original rom instead of a board which looks the same, but probably have a own vendor version of it.

For the cyrix cpus, didnt know that.. But probably would use and Intel DX 33 anyway.