DarthSun wrote on 2024-03-02, 17:00:

I made a comprehensive S7/SS7 test from 100-617MHz, which is why I used Epox. FSB/multiplier can be practically varied + a video […]
Show full quote

JustJulião wrote on 2024-03-02, 12:26:

Epox boards of that era rock!
I have the Baby AT version of yours but I didn't test the W2 on it.

I made a comprehensive S7/SS7 test from 100-617MHz, which is why I used Epox. FSB/multiplier can be practically varied + a video card that didn't even exist back then, I like such extremes. I have the image backups, I thought it might be interesting. I tuned each CPU to a clock rate that is stable even with continuous use.
For example, a graph from the test:
3dm99.jpg

Wow the Winchip 2A @2.5x100MHz has quite a solid position clock-for-clock in your chart!

BitWrangler wrote on 2024-03-02, 17:15:

Was that a 2.2V MII at 2.5 x 100? Because it's odd it didn't score level with the 6x86mx at 2.5x100 otherwise. We've been speculating as to whether the core shrink added some latencies to try to get higher clocks.

No, 2.9V black. Back in the day it was Gold for me, but now I was curious about the black one.

There is a small difference between them, overall the MII achieved a slightly better result.

There is a PR400 from 18 microns in the machine, but I was too lazy to take it out for the test, it is packed away.

This instance runs 336, but I tested it with an even slower video card -FX5950Ultra-, the result is not directly comparable.

JustJulião wrote on 2024-03-02, 17:16:

DarthSun wrote on 2024-03-02, 17:00:

I made a comprehensive S7/SS7 test from 100-617MHz, which is why I used Epox. FSB/multiplier can be practically varied + a video […]
Show full quote

JustJulião wrote on 2024-03-02, 12:26:

Epox boards of that era rock!
I have the Baby AT version of yours but I didn't test the W2 on it.

I made a comprehensive S7/SS7 test from 100-617MHz, which is why I used Epox. FSB/multiplier can be practically varied + a video card that didn't even exist back then, I like such extremes. I have the image backups, I thought it might be interesting. I tuned each CPU to a clock rate that is stable even with continuous use.
For example, a graph from the test:
3dm99.jpg

Wow the Winchip 2A @2.5x100MHz has quite a solid position clock-for-clock in your chart!

Yes, it was a great result.

DarthSun wrote on 2024-03-02, 18:06:

No, 2.9V black. Back in the day it was Gold for me, but now I was curious about the black one. MII300Black.jpg 6x86MXBlack.jpg T […]
Show full quote

BitWrangler wrote on 2024-03-02, 17:15:

Was that a 2.2V MII at 2.5 x 100? Because it's odd it didn't score level with the 6x86mx at 2.5x100 otherwise. We've been speculating as to whether the core shrink added some latencies to try to get higher clocks.

No, 2.9V black. Back in the day it was Gold for me, but now I was curious about the black one.
MII300Black.jpg
6x86MXBlack.jpg
There is a small difference between them, overall the MII achieved a slightly better result.
MIIvs6x86MX.jpg
There is a PR400 from 18 microns in the machine, but I was too lazy to take it out for the test, it is packed away.
MII400Gold.jpg
This instance runs 336, but I tested it with an even slower video card -FX5950Ultra-, the result is not directly comparable.

Thanks a lot for the details. I guess it isn't really a significant difference, lose it in the run to run variance noise.

BitWrangler wrote on 2024-03-02, 19:04:

DarthSun wrote on 2024-03-02, 18:06:

No, 2.9V black. Back in the day it was Gold for me, but now I was curious about the black one. MII300Black.jpg 6x86MXBlack.jpg T […]
Show full quote

BitWrangler wrote on 2024-03-02, 17:15:

Was that a 2.2V MII at 2.5 x 100? Because it's odd it didn't score level with the 6x86mx at 2.5x100 otherwise. We've been speculating as to whether the core shrink added some latencies to try to get higher clocks.

No, 2.9V black. Back in the day it was Gold for me, but now I was curious about the black one.
MII300Black.jpg
6x86MXBlack.jpg
There is a small difference between them, overall the MII achieved a slightly better result.
MIIvs6x86MX.jpg
There is a PR400 from 18 microns in the machine, but I was too lazy to take it out for the test, it is packed away.
MII400Gold.jpg
This instance runs 336, but I tested it with an even slower video card -FX5950Ultra-, the result is not directly comparable.

Thanks a lot for the details. I guess it isn't really a significant difference, lose it in the run to run variance noise.

Yes, it might just be measurement deviations.

Chkcpu wrote on 2024-02-27, 12:55:

Hi all, […]
Show full quote

Hi all,

I received several requests for changes to the QDI Titanium IB+ BIOS. So I have been working on a patch J.3 BIOS update for this jumperless board, and I made some progress.

@JustJulião,
I was able to add IDT WinChip 2/2A/2B support. The new BIOS now properly detects these IDT models and displays them correctly as IDT WinChip 2.
The SpeedEasy CPU SETUP code is very difficult to change so the multiplier settings are still the same as for the WinChip C6 but they work the same way on the WinChip 2 and 2B. Only for the WC-2A, you have to use the translation table I put up earlier in this thread, when setting the multiplier.

@S0N1C,
I read your request about Tillamook support and I’ve started to look into that.
The BIOS detects and displays the Tillamook just fine but support for this CPU is completely missing in the SpeedEasy CPU SETUP, just as you reported. Instead, the BIOS sets the board as for a standard non-MMX Pentium with a single voltage rail with 3.4V! 🙁

The first step will be to change this to a dual voltage Pentium MMX setup. This shouldn’t be too difficult. But secondly, the default 2.8V setting for the MMX has to be lowered to 2.0V for the Tillamook only. This will be a challenge…
Note that the 2.0V Vcore and 3.3V Vi/o are the lowest possible settings on this board due hardware limitations.

@Sphere478,
You did the interposer for the Tillamook and other socket 7 CPUs, so could you help us with the multiplier settings on the Tillamook? Without hardware changes, this jumperless QDI BIOS can control the BF0/BF1 pins of the original Pentium MMX only. The Tillamook BF2 is therefore out of reach without an interposer.
Can you tell us which multipliers are possible on the Tillamook by using these original BF0/BF1 pins only?

To all,
Other bugfixes that I will add to the patch J.3 BIOS:
- A fix for the second 64GiB HDD limit bug. This will fix a hang when initiating drive detection via the IDE HDD DETECTION menu in the BIOS on a drive > 64GiB.
- An improved 32GiB HDD limit bugfix that allows drives > 128GiB to be attached, so at least 128GiB can be used from a larger drive (maximum 640GiB).
- A fix for the Win98 UDMA bug. This allows ATA66/100/133 drives to work correctly in UDMA mode 2 (33MB/sec) on the on-board IDE channels by enabling DMA mode in device manager. Without this fix, these faster drives would revert to PIO mode 4.

I will be back with an updated progress report soon. 😉
Jan

Hi all,

It’s been 5 weeks since I promised a new patch J.3 BIOS for the QDI Titanium IB+, so high time for an update. 😉

Reverse engineering the SpeedEasy CPU Setup menu logic in this jumperless BIOS proved to be educational. I salute QDI’s BIOS engineers for this innovative piece of software.

Yes, there is a story here.
When patching a compressed socket 7 Award BIOS, I only made changes in the compressed main module (original.tmp) and its BIOS extension helper module (Awardext.rom), until now.
Looking at the main BIOS module, where most POST routines and all the BIOS Setup menus are located, I did find the logic, data structures, and associated CPU detection for the SpeedEasy menu. For the patch J.2 BIOS from 2003, this is where I made a simple change to include the K6-2+/K6-III+ in the SpeedEasy menu. However the low level logic that this jumperless motherboard needs to directly talk to the hardware for CPU voltage, FSB, and multiplier control was nowhere to be found.

So I started looking at the Bootblock code in the uncompressed part of the BIOS. Together with the ESCD block and the decompression engine, this initial boot code takes up the top 20KB of this 128KB BIOS. The remaining 108KB code space is for the compressed modules.

I never had to analyze and patch a Bootblock before, so disassembling this code was a new experience. The tightly packed boot code in the 8KB Bootblock didn’t show any room. But the 4 KB block of the decompressing engine had some space left and indeed, there I found the missing low level code of the SpeedEasy CPU Setup!

In hindsight, this is a logical place to put the low level jumperless control. It provides very early control during bootup for setting Vcore and allows a quick reboot for a changed multiplier setting. The CPU only samples the BF2/BF1/BF0 pins when coming out of reset and disregards any changes thereafter.

Because the SpeedEasy_exec code (as I call it) in the Bootblock is executed before any compressed modules are decompressed in RAM, it cannot “talk” to the SpeedEasy code in the main BIOS module. Passing CPU Setup information from the POST routines to the Bootblock is all done via CMOS registers that retain this information during reboot or power cycle. Clever.

@JustJulião,
Armed with these findings, I started patching for WinChip 2 support. Changes in the J.3 BIOS are:
- Added detection of the WinChip 2(A)(B) CPU
- Expanded the CPU Type display for showing the correct IDT WinChip 2 string
- Added proper X2.5, X3, X3.33, X3.5 multiplier selections for the WinChip 2A in the SpeedEasy CPU Setup (Jumper Emulation mode)
These additional changes are also done:
- The improved 32GB HDD limit bugfix
- A fix for the second 64GB HDD limit bug
- A fix for the Win98 UDMA bug

After finding-out how to change the Bootblock without triggering a BIOS checksum error, I made an additional change to the SpeedEasy_exec code.
- I expanded the K6 model 7/K6-2 CPU protection against a too high Vcore, to include the K6-III/K6-2+/K6-III+ models. This logic resides in the Bootblock at the end of the first POST step (C0) and protects the CPU when the BIOS hangs early during POST due to BIOS corruption or failed/missing RAM.

CAUTION: The above means that you have to flash the patch J.3 BIOS WITH Bootblock!

Here is the new QDI TIB+ patch J.3 BIOS for you to try-out.
http://www.steunebrink.info/bios/T1BP_J3.zip

I’m curious how it works with your WinChip 2A, specifically the SpeedEasy multiplier selections.

@S0N1C,
I also did the extensive Bootblock analysis in view of better Tillamook support.
The change to have the Tillamook detected as a dual voltage Pentium MMX in the SpeedEasy CPU Setup works fine in this patch J.3 BIOS, but I was unable to lower the lowest Vcore from 2.8V to 2.0V.
At the moment I lack the time to investigate this further, so I hope you have another board to run this nice Tillamook CPU.

Cheers, Jan

thank you for trying!
yes, I was testing it in Soyo SY-5EHM and it seem to run fine at 2.3V 112 MHz FSB, so 450 MHz core 😀 and AGP gives more choice for the video cards. Still, I would probably build another system with this QDI board and different CPU.

"CPU protection against a too high Vcore, to include the K6-III/K6-2+/K6-III+ models" - so it would just shutdown? 2.8V is the minimum voltage that is now possible?

S0N1C wrote on 2024-03-22, 20:53:

"CPU protection against a too high Vcore, to include the K6-III/K6-2+/K6-III+ models" - so it would just shutdown? 2.8V is the minimum voltage that is now possible?

Because the motherboard hardware can generate Vcore voltages from 2.0V to 3.5V, a BIOS corruption could damage a CPU by inadvertently commanding a too high voltage.
The protection against a too high Vcore was build in the Bootblock to protect AMD 2.2V CPUs by limiting Vcore to 2.2V when the BIOS hanged. The change I made only extends this protection to other 2.0V-2.4V AMD models.

When the system is operation normally, this protection is taken over by the regular Vcore control in the BIOS.

Because all other CPU models this BIOS knows need 2.8V Vcore or higher, a protection for non-AMD CPUs was not implemented.
So no protection for the Tillamook, but the minimum voltage for the Tillamook is now 2.8V in the patch J.3 BIOS.

Jan

Understood, thank you. Is it maybe possible to make board think that Tillamook is an AMD K6-2+? Probably not...

S0N1C wrote on 2024-03-22, 22:11:

Is it maybe possible to make board think that Tillamook is an AMD K6-2+? Probably not...

Although this would fix the low Vcore for the Tillamook, this is not a good idea.
Intel and AMD CPUs have a different set of Machine Specific Registers to enable and configure their various features. So when later during POST the BIOS tries to configure Write-Allocation for the K6-2+, it will hang with an illegal opcode exception because the Tillamook doesn’t have these MSR’s.

I’ve now started work on the similar QDI Titanium IIB SpeedEasy BIOS.
When I have the time, I will look again for a proper low Vcore fix for the Tillamook on both these TIB+ and TIIB boards.

Nice that you could get the Tillamook up to 450MHz on your SY-5EHM board.
Must be a record! 😉

Jan

Could you trick tillamook as detecting as a k6-2 2.2v maybe? It would be wrong, but votlage would be safer. Edit, I see this was already asked

Can you post these findings in the diy modding guide thread? 😀

Btw, is 2.2v cyrix detection working? What about 2.0v rise?

Sphere478 wrote on 2024-03-23, 19:11:

Btw, is 2.2v cyrix detection working? What about 2.0v rise?

Hi Sphere,

Looking at the Cyrix 6x86 support in this jumperless QDI IB+ BIOS, I see a 3.4V default for the original single voltage Cx6x86, 2.8V Vcore for the dual-voltage Cx6x86L, and 2.9V Vcore for the 6x86MX.
So no 2.2V support for the later MII version.

Rise CPU support is totally absent in this BIOS. Not surprising for a mid-1998 BIOS core. 😉

Although I find the design fascinating, I’m not a fan of these jumperless boards. The BIOS is often too limiting when you want to use later CPU models, that would otherwise run fine had the board used the traditional jumpers.
I will take boards with their plethora of jumpers any day! 😀

Cheers, Jan