Do you mean the SSE2 instructions? I don't think there is anything particularly special about "netburst" other than maybe the bandwidth that rdram provided (something that quake3 loved).

I don't think there ever was a specific way to program for an early P4 in order to make it faster than a late P3.
The only real advantage the P4 had (in its early form) was SSE2 and more memory bandwidth. Regarding SSE2, yeah, one could specifically take advantage of it when programming, but by the time SSE2 was extensively used in games, Willamette had already been obsolete for a long time.

The Netburst architecture was all about Intel planning ahead for the future. The architecture with its 20 stage instruction pipeline (on Willamette) was less efficient than that of the P3, but it could better scale in frequency (or so Intel thought, until they realized that heat had become a serious problem).

As a fun fact, Quake 3 (which was never specificially programmed for the Netburst architecture), actually ran better on the P4 since the beginning, but nobody knew why, not even John Carmack.

Netburst was unusually sensitive to optimization, so I think it's plausible that a carefully programmed game would narrow the "per-clock" performance gap between it and P3. I have no idea what games, if any, make a good demonstration of this though. I presume the P4s relative performance should have improved when newer compilers were released or when programmers took the time to write in assembly.

I think that higher priced professional software (CAD and whatnot) was where programmers would invest the most time and effort into this, and they were targeting the P4 pretty specifically.

Philosophically I have some sympathy for what Intel was trying to do, in designing a CPU that had the potential to be very fast if the code for it was written carefully. In that sense I disagree with the popular notion of Netburst being a "brute force" approach. I perceive it as meaning to be elegantly powerful but it relied heavily on software being written to work with it smoothly, so it could stay on the throttle and not have to dump the pipeline too much.
I think by the 2000s not many programmers (or the companies that employed them) wanted to invest as much time into optimization as they would have say 5-10 years prior.

Another issue though is that by the 2000s there's a lot of enhanced craziness going on in superscalar x86 CPUs that the programmer can't directly control even in assembly. It's more difficult (and I imagine frustrating) to optimize when the CPU's performance depends on features that can't be taken out of autopilot. It was like assembly had become deprecated to where it no longer served it's original purpose of giving the programmer full control over the CPU.
I think Itanium attempted to address that, but it went nowhere.

Now when you get to Prescott, yeah I call that brute force.

mwdmeyer wrote on 2021-03-28, 09:21:

Do you mean the SSE2 instructions? I don't think there is anything particularly special about "netburst" other than maybe the bandwidth that rdram provided (something that quake3 loved).

What about a Pentium 3 with RDRAM?

As far as Netburst... Bleh. The pipeline was too long and from what I understand, Intel designed it that way because they wanted to eventually get the clock speed to around 5Ghz if memory serves.

The Netburst design didn't pan out like they wanted it to which is why they essentially went back to the P3 design with the Core series.

Or am I wrong here? It has been quite a while since I did research on it.

cyclone3d wrote on 2021-03-28, 16:45:

What about a Pentium 3 with RDRAM? […]
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mwdmeyer wrote on 2021-03-28, 09:21:

Do you mean the SSE2 instructions? I don't think there is anything particularly special about "netburst" other than maybe the bandwidth that rdram provided (something that quake3 loved).

What about a Pentium 3 with RDRAM?

As far as Netburst... Bleh. The pipeline was too long and from what I understand, Intel designed it that way because they wanted to eventually get the clock speed to around 5Ghz if memory serves.

The Netburst design didn't pan out like they wanted it to which is why they essentially went back to the P3 design with the Core series.

Or am I wrong here? It has been quite a while since I did research on it.

Yeah, the Pentium M and the very first Core branded CPU (the 32-bit "Yonah" Core Duo, which was basically two PM cores) are very similar to Tualatin, right down to cache latency and bandwidth per cycle (at least according to cache benchmarks I've done). Saying that Pentium M is a souped up Tualatin with SSE2 support and a QDR bus doesn't appear to be that far from the truth!

However, I believe Core 2 was actually quite different from P6/Pentium M, with its 64-bit support, 128-bit SIMD unit, and much faster caches.

mwdmeyer wrote on 2021-03-28, 09:21:

I don't think there is anything particularly special about "netburst" other than maybe the bandwidth that rdram provided (something that quake3 loved).

Even that's more of a chipset thing rather than a netburst thing. Intel didn't integrate their memory controller up until the Nehalem. And there is for example the VIA Apollo Pro 266 for the Pentium III with DDR support and the Intel i840 and i820 chipsets with RDRAM support.

How about an Athlon 1400C with DDR266/333? The P3 1400S just came out pretty late in the grand scale of things and was quite pricier than any Thunderbird/AthlonXP chip. Besides, most motherboards around didn't support it natively, which meant either building a new system or sourcing an FCPGA2 adapter just to upgrade to an outdated platform.