First post, by Madao
Story: I am make thougt about ViRGE VLB video card, since i did found a datasheet of S3 ViRGE (86C325). This 3D Deaccelerator has VLB-interface, we didn't see one ViRGE card with VL-interface. I make a 968VL card , because i want a card with 4MB VRAM, it is top on line for VLB-system -> S3 Vision 968 VLB replica
People tell me: MAKE ViRGE VLB , Making a Concurrent for Creative 3D Blaster VLB (thanks Matze79 )
A introduction of me: i am electronics technican, but no study. Just a electronic.
I got first in 1997 PC from dumpster diving, a 386SX PC, but it is dead ... , it is parted out.
Second dumpster dived PC is a 486DX 33 with 486UL motherboard, 16MB RAM, Trident TVGA8900, 504MB conner harddisk. I was 10 years old and it happens in year 1997/8(not sure).
This PC has strange job: a computer for blind people with braille - keyboard, but i can't use him.. and hobby is born, many thinkering and adventures with this computer. 😉 How got i this strange computer: I live on old blind boarding shool, while i visit deaf shool.
Now a introduction of project...
A member has STB powergraph 64 video, a Trio64V+ VLB card, it is rare card. Why Trio64V+? ViRGE 325 is full compatible with Trio64V+ pinning.
I got good pictures, thanks cyclone3d. -> Re: S3 Vision 968 VLB replica
I thougt at first: oh no, Trio64V+ runs into Trio64 compatible mode, because i see only one decoder with NOR-gate.
Explain: Trio64 and ViRGE is not compatible, too difference pinout, but Trio64V+ can switched to Trio64 pinout. (config strap resistor). ViRGE lacks this feartures and has same pinout with Trio64V+ in LPB-mode (standard).
Idea with modification a Trio64 to ViRGE, sadly not possible.
I make a notice about their trace: YEAH, it runs in LPB-mode and SAUP2 is wired direct to address line 30.
here a scanned notice.
SAUP1 is asserted in 0-8MB i/0 address range, and it morrored at 128 ; 256 ; 384MB address range. (also it replay same with 2GB offset)
SAUP2 is asserted in 1 & 3 GB I/O address range, not at 1024MB (there is SAUP1 also asserted.) -> above 1032MB Address range.
It is enough for most 486 PC. (most haven't more than 16MB memory, except our retro mania 😉 )
My concept (minimalizied design), need only two TTL (74F245 and 74F260 ), but i would make others with address decoder.
Next step: I have two Trio64 card , one VL, one PCI, both cards came from same company "SPEA"
I must make notice about their trace with SAUP (Trio64 VL use SAUP decoder.) address range and swap their ROM.
If PCI-ROM doesn't run on Trio64-VLB card. This procjet is then shut down. My ability by software is not so good. ( huge ROM modification is very heavy job for me)
I have a hope.
Pleas give me time, this stuff is storaged in parents farm. (no, not a barn as storage 😉 )