VOGONS


First post, by llm

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this is disassembled from a game

mov dx, 3C4h
mov ax, 0F02h
out dx, ax
mov dl, 0CEh
mov ax, 3
out dx, ax
mov ax, 205h
out dx, ax
mov al, 8
out dx, al

ported to C with some infos i've found

https://fd.lod.bz/rbil/ports/other/p03c403c5.html
03C4 -W EGA TS index register
https://fd.lod.bz/rbil/ports/video/p03ce03cf.html
03CE -W EGA GDC index register

the above assembler is to my understanding this:

                         p: 0x3C5  p:0x3C4
outw(0x3C4, 0xF02); // 0b00001111_00000010 -> writes also 0x3C5
0xF 0x02
| |
| Map mask register
|
Write enable display memory plane 0..3

https://fd.lod.bz/rbil/ports/video/p03ce03cf.html#table-P0700
p:0x3CF p:0x3CE
outw(0x3CE, 3); // 0b00000000_00000011 -> writes also 0x3CF (3 = data rotate register, rotate-count=0, CPU-data overwrites) https://fd.lod.bz/rbil/ports/video/p03ce03cf.html#table-P0703
outw(0x3CE, 0x205); // 0b00000010_00000101 -> writes also 0x3CF (5 = mode register, mode2, plane source is CPU as set/reset) https://fd.lod.bz/rbil/ports/video/p03ce03cf.html#table-P0704
outb(0x3CE, 8); // 0b 00001000 -> writes only 0x3CE (8 = bit mask register, ???)
Index
00000010

is that correctly interpreted?

Reply 1 of 3, by cinnabar

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You might want a better EGA reference, but yes this seems correct.

Programmer has enabled all four maps in the map mask register of the Sequencer
Then set data rotate as zero in the GC.
Then set write mode 2 in the GC
Then has selected the bit mask register in the GC

Reply 2 of 3, by llm

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thanks

cinnabar wrote on 2023-06-26, 17:13:

You might want a better EGA reference

this mame source seems to be also helpfull to me: https://github.com/mamedev/mame/blob/master/s … bus/isa/ega.cpp

and for the last line

outb(0x3CE, 8);

the the 0x3CF port still contains the 0b00000010 from the former write?

Reply 3 of 3, by mkarcher

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llm wrote on 2023-06-27, 12:57:
and for the last line […]
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and for the last line

outb(0x3CE, 8);

the the 0x3CF port still contains the 0b00000010 from the former write?

The 3CF port does not contain a value. It provides a window to one of the nine values stored in the graphics controller. The 3CE port contains a value, and selects what register is visible when you access the 3CF port. The last line just selects that accesses to the 3CF port that will occur later are targetting the bit mask register. It does not change the bit mask register. When you read 3CF (on a VGA card; EGA doesn't support reads), you will read the last value written to the bit mask register, which might be 2, but most likely is 0FFh, the default value of the bit mask register.

The EGA BIOS functions always leave the bit mask register selected, so some EGA software assumes that it can write to 3CF and target the bit mask register without writing anything to 3CE. The point of the last outb is to restore this default state of the EGA card configuration, not to achieve any immediate effect.