I used to get that too actually in my emulator. Keyboard seemed to work fine except EDIT and Police Quest where for any key I would press I would get a '. I do not remember the fix precisely but it was related to setting up the 8255 (and 8042) to mark key processed. I think once the user/BIOS requested the key via port 60 I had to clear the interrupt line basically saying: no more key.

However, 8042 does not exist in an XT machine, only in AT machines. I do not know how your emulator works but you have to be careful what pieces you put together ( in terms of HW) because the the Generic Turbo XT will not expect an 8042 but rather an 8255 and not interact with it properly. In my emulator if I want a XT machine (or a PCJr) I have an 8255 otherwise I have an 8042 (for a 286 or a 386 PC, with a correct BIOS).

Regards,
Vlad.

Is there any information on programming/emulating such a keyboard somewhere? I can only find info on the PPI and PS/2 keyboard on osdev. Any info about that XT keyboard controller you've mentioned?

PPI is just another name for the Intel 8255 chip. The ports are here: http://bochs.sourceforge.net/techspec/PORTS.LST. You only need to implement 0x60-0x63. Also check out PCEm's implementation of the 8255/PPI chip (for XT, they have a separate one for PCJr).

I already have those ports mostly implemented (Both XT and AT version). IRQs are generated during hardware buffer fills and when port 0x60 is read (function fill8042_input_buffer). Only the keyboard acnowledge is still unsupported(Saved like the rest of the byte). Port 60h currently receives receives/sends data to the keyboard/mouse, using the 8042 controller(keyboard at port 0, mouse either connected to aux port or serial port(set in BIOS menu by the user). So afaik only port 0x61 has required bit 0x80 unsupported(keyboard acnowledge). So I should add support for that bit on 80(1)86 PCs(using XT BIOS) to clear input buffer(and receive next if available and set irq1 if enabled) when it's received instead of when reading port 0x60? So act like a PPI instead of a full 8042?

Also, does the 0x80 bit set need to be cleared when processed (input buffer cleared)?
https://bitbucket.org/superfury/x86emu/src/bd … ppi.c?at=master
https://bitbucket.org/superfury/x86emu/src/bd … 042.c?at=master

Btw the input buffer is from the perspective of the CPU, not as the manuals say from the perspective of the 8042.

Afaik with PPI (8255 at ports 60h-63h) the motherboard has a serial shift register that can only receive one byte from the keyboard, and then it will jam further communication from the keyboard by jamming one of the wires low and also this will trigger a pending IRQ1. The BIOS int9 routine can then freely go read port 60h as many times as it wants and the data byte stays the same, and only when the port 61h bit 7 is set high and low the pending IRQ1 goes away, the shift register data is cleared to zero and the keyboard wires are let back to idle state so next byte can be received by the motherboard. So yes, the XT bios will use bit 7 of port 61h. Most likely this stuff is similar with PC, XT and AT, but I am mostly familiar with original IBM PC 5150 schematics and Amstrad PC1512/PC1640 schematics.

In case of 8042 keyboard controller on motherboard, it sits on ports 60h and 64h, and few bits of port 61h is implemented elsewhere for compatibility like bits 0&1 for speaker and the timer counter outputs. The BIOS will know about the 8042 and it will only read port 60h for keyboard data, but it won't toggle the port 61h bit 7, because reading port 60h will pop the value from keyboard controller and drop the IRQ1, so that next bytes just cause more IRQ1s.

I also think 8042 has a few byte FIFO for keyboard data, so it is an input buffer from the keyboard, inside 8042, which will then gets emptied by x86 CPU. Well semantics, it could be also called output buffer towards x86 CPU.

Also some old games (like Monkey Island) that do hook keyboard interrupt will toggle 61h bit 7 because PPI needs it, but it will work with 8042 too, so I think it does no harm, even though on these modern times the bit could be reserved for NMI control or something.