That's not what I mean. Does the CPU use an internal register to store the data for/from RAM, or does it exploit the data bus retaining the value by performing a read/write at the same time like DMA does? So write to memory at the same clocks while the hardware supplies tje data lines the very same clocks?
E.g. assert both IOW and MEMR or IOR and MEMW at the same time(performing a read directly into RAM without buffer or write from RAM directly), in just a few cycles(like DMA does)? Does it use internal buffers to store the data, or does it exploit the data bus like DMA does?
So, from https://docs.freebsd.org/doc/2.2.6-RELEASE/us … andbook293.html :
The floppy disk controller is now responsible for placing the byte to be transferred on the bus Data lines. Unless the floppy controller needs more time to get the data byte on the bus (and if the peripheral does need more time it alerts the DMA via the READY signal), the DMA will wait one DMA clock, and then de-assert the -MEMW and -IOR signals so that the memory will latch and store the byte that was on the bus, and the FDC will know that the byte has been transferred.
Simply let the hardware fill the data bus and the other side read it, like DMA does? Thus no CPU buffers?
Edit: Or is this impossible due to only having one address bus for both IO and MEM? DMA only needs one(the device being addressed using DACK instead)?