I've just been thinking: the 'buffer full' bit that's documented in the DSS documentation(bit 6 of the LPT status register)... Could it be that it's sticky? With that I mean that it changes from 0 to 1 when the buffer becomes full, but doesn't become 0 again(triggering an IRQ when it's enabled on the LPT) until the buffer is either fully emptied by rendering or a new value is added to the buffer(which re-checks said bit and updates it for compatiblity)?
So in that way, both the detection scheme(becoming 1 when full) and the entire 16-byte buffer can be used during the rendering of sound(instead of throwing an IRQ for every sample that's sent to the DAC(since the ACK line becomes 0 after the first byte is emptied from the buffer))?

Edit: I've tried to implement it this way:
- When a byte is written, the full flag is cleared, making it instantly become the current full status(see below).
- When the status(ACK in this case) is read, if the buffer is full, the flag is set(giving full status). Else, if the buffer is empty, it's cleared(giving empty status).

So when software tries to do single-sample transfers each time, the full status will update every time a byte is written, setting the flag(because the buffer became full) when data is added, as is documented(also allowing detection schemes to work).
But when the program wants to use the full capabilities of the FIFO, it just writes until the flag becomes set(since the buffer was full), which won't become empty until all samples are rendered(buffer is empty), at which point the flag clears and the IRQ is triggered. It should also work with the code written in the documentation of the DSS.

Would that be correct behaviour?

OK. Testing the parallel port emulation with the Sound Source, I noticed something: it seems like Wolfenstein 3D doesn't turn off the Sound Source connected on the parallel port(upon exiting, it leaves bit 2 of the control register set, thus leaving the Sound Source powered on? I also see MS-DOS enabling it somehow when booting?

Or is that perhaps an issue with the Compaq Deskpro 386 BIOS?
Edit: The same thing happens with Windows 95 booting. Just before booting, it's turned on?

Hmmm... Those weird values writing into the parallel port's control register seems to be due to the INT 17h or some part of the BIOS handling of interrrupt 17h? That's not supposed to happen? So there's some CPU bug there?

Edit: Just confirmed. It's the initialization call of the BIOS, INT 17h function 01h DX=0 (http://www.ctyme.com/intr/rb-2099.htm) that's causing the DSS to turn on on boot.

So, somewhere in there, there's a CPU or hardware(most likely CPU) error?

Edit: Hmmm... So this seems to be the entirety of the code that enables the DSS speaker while booting:

Somewhere in there, there might be something wrong when running in UniPCemu. Or perhaps it's a basic issue with said BIOS itself?

This is what runs:

This is what I can conclude so far:

Just took another look at the DSS schematic (https://archive.org/details/dss-programmers-g … age/n3/mode/2up page 5)... It looks like the output signal of the buffer is actually NOT FULL, which drives a transistor to ground pin 10 when set.
So when the device is turned on and the buffer is not full, said signal is set and pin 10 is grounded( thus the input becomes 0 ).
If the device is turned off (pin 17=low because the chip can't drive it) or the buffer is full(chip is driving it low), said signal is effectively 0, causing the transistor to not ground pin 10(ACK). Then, the value becomes the input of line 16 instead(=line 16, the INIT line). So in that case, ACK=INIT.

So only in the off state and in the on state with full buffer, pin 10(ACK) becomes INIT because it isn't grounded. But pin 10(ACK) is flipped on the PC side, causing it to be inverted.

So, from the output pins(raw output signals on SELECT/INIT lines) until the input pins:
- Off(SELECT(pin 17)=0), pin 16(INIT not grounded)=>10(ACK), ACK is reversed so: ACK=!INIT
- On(SELECT(pin 17)=1) with full buffer(INIT not grounded): same as the off state, pin 16(INIT)=>10(ACK), ACK is reversed so: ACK=!INIT. So when INIT=1, ACK=0 and when INIT=0, ACK=1.
- On(SELECT(pin 17)=1) with not full buffer: INIT is grounded(becomes 0 always), then reversed on read, so ACK=1 always.

So in all cases, ACK=!INIT, except when SELECT is set with a not full buffer(which according to me is actually more like a "was not last full" flag instead of a is isn't full flag, meaning the definition of full/empty is simply the last full/empty state being reached) where INIT is grounded and ACK is 1 always.

Edit: So the INIT line is active low, so the value 0 being in the INIT bit becomes 1 to the ground, while the value 1 being in the init bit becomes 0 to the ground. So only when INIT isn't set, the buffer status can become 1 or a 0 when grounded.

There is just something fascinating about such a relatively simple device as the Disney Sound Source, wouldn't you agree? 🙂

Any way, I remember perusing through the official programming guide (which you can find at archive.org) and I believe the DSS never triggers an IRQ. The designers could have chosen to use the IRQ on the parallel port as a means to signal the host PC that the FIFO was full, but for some reason they chose not to, and decided to go with a status pin instead.

Maybe because not all parallel port implementations included an IRQ? Or maybe because it wasn't necessary, since the programmers were expected to continously monitor the status pin and keep the FIFO buffer fed in a backround routine piggy-backing on the system timer interrupt anyway, so triggering a hardware interrupt in addition to that would have been redundant?

I think it's probably just meant to keep the FIFO full using a background process? And the only reason there's said full/not full bit instead of an completely full/completely emptied bit is to supply data into the FIFO in an OS-style? So use the FIFO full bit only to keep the cache as full as possible, much in the same way the Prefetch Input Queue(PIQ) of the x86 works best when continuously being completely filled? That's the only reason I can think of. Otherwise, couldn't they just implement the completely full(1)/completely empty(0) bit on the ACK line for parallel port IRQs and use the SelectIn pin(which is grounded with the DSS) as the FIFO full/not full bit instead? That would allow both methods to work?

Afaik all pins other than ACK in the status register are grounded or passthrough anyways?
Thay's error(pin 17, grounded externally and used to drive chip select), select_in(pin 15, passed through), paper_out(pin 12, passed through), busy(pin 11, passed through)?