I've modified and adjusted that little loop by adjusting the 80286 (actually 8086 timings) so that the count ends up with exactly F952 ticks counted. It now correctly continues without erroring out at the DRAM Refresh speed test (ending up with a '8086' at 7280500Hz).
Edit: It now gets up to this point (A bit over 6MB memory is installed because of the autodetect):
2xx Memory (RAM) Errors
xxyyyy yyzz 201 bad ram chip in bank xx row zz
So that's bank 20h, row FF? What memory address is that?
Edit: Whoops, my MMU was repeating the 640K ISA memory hole above 1MB. So any part above 1MB where the 640K limit (1640K-2M, 2640K-3M, 3640K-4M etc.) was matched was redirected to a memory hole 😖
It now gets to the top of memory (Exactly 6MB installed) and errors out:
106144 KB OK 2 3660000 FFFF 201-Memory Error
This matches the end-of-RAM in my emulation (Exactly 6MB is installed, with the memory buffer area from 640K-1M being inserted at 1M+, thus adding 0x60000 memory bytes on top of the normal extended memory).
I've currenty implemented the 640K memory hole at 640K-1M and high memory hole at the last MB. But any memory in between is skipped (the memory holes are added to the memory after 1MB). Is that correct?
Edit: After changing the memory to simply ignore writes to those invalid ranges and give 0xFF on reads, it now passes the first check. Then it gets to:
105760 KB OK 2104-System Board Error
Edit: Enabling the memory from 640K-1M to be added (mapped to 1M+, with the 1M+ memory being mapped directly after it) increases this to "06144 KB OK". The 104-System Board Error still occurs? Anyone knows why this happens? First it tests the full memory range. Then it tests it again, only to fail when the end of memory is reached?
Looking at the end of the diagnostic log debugger.txt createn:
100:13:39:28.03520: POST Code: 31 200:13:43:74.04768: POST Code: 32 300:13:44:82.00032: POST Code: 31 400:13:49:21.08496: POST Code: 32 500:13:50:34.03104: POST Code: 31 600:13:54:74.03424: POST Code: 32 700:13:58:06.07648: POST Code: 33 800:15:25:34.03424: POST Code: 34 900:15:25:34.05920: POST Code: F0 1000:15:25:34.06048: POST Code: 81 1100:15:25:36.06848: POST Code: 85 1200:15:25:36.06912: POST Code: F1 1300:15:25:38.04960: POST Code: 00
So it enables real mode again, then "Data Segment Set", Descriptor table built, 85?, Exception interrupts tested, then 00?
Edit: The problem seems to be now, that the first interrupt called (interrupt 10h) executes a triple fault, because the Present bits of all exceptions (including the INT call itself)) is 0?
The descriptor called during the INT 20h contains D01C400000860000(low to high bytes of the descriptor). So it contains:
Offset: 1CD0
Selector: 4000
Type byte: 86
The type byte says:
Gate type: 6
Storage: 0
DPL: 0
Present: 1
But, for some reason, the software debugger says Present=0?
Edit: Looking at the typedef of the IDT descriptor: it's backwards. Thus the data was being decoded incorrectly(big endian instead of little endian).
The test still doesn't pass, although the IDT should have been fixed now.
It currently tests the limit check, although with limit checks enabled it might not make it all the way (currently status 21h).
1MOV AL,9DH ; SET INTERRUPT 13 FLAG 2 OUT DMA_PAGE+0AH,AL ; FOR THE INTERRUPT HANDLER 3 4;----- MODIFY DESCRIPTOR TABLES 5;----- SET TEMPORARY ES DESCRIPTOR TO SEGMENT LIMIT 6 7 MOV DS:ES_TEMP,SEG_LIMIT,0 ; SET SEGMENT TO 0 8 9;----- CPL0, DATA ACCESS RIGHTS 10 11 MOV BYTE PTR DS:(ES_TEMP.DATA_ACC_RIGHTS),CPL0_DATA_ACCESS 12 MOV BYTE PTR DS:(ES_TEMP.BASE_HI_BYTE),01 ; DO ALL TESTS ON 2ND 64K 13 MOV WORD PTR DS:(ES:TEMP.BASE_LO_WORD),0 14 15;----- SET ES REGISTER 16 PUSH BYTE PTR ES_TEMP ; LOAD ES 17 POP ES 18 19;----- CAUSE AN EXCEPTION 13 INTERRUPT 20 SUB DI,DI 21 MOV AX,ES:[DI] ; THIS SHOULD CAUSE AND EXCEPTION 22 SUB CX,CX ; WAIT FOR INTERRUPT 23LOOP2: IN AL,DMA_PAGE+0AH 24 AND AL,AL ; DID THE INTERRUPT OCCUR? 25 LOOPNZ LOOP2 26 JZ T7_3 ; CONTINUE IF INTERRUPT 27 JMP ERROR_EXIT ; MISSING INTERRUPT
This cannot cause an exception? Even though the limit is zero, access to byte 0 in the segment(ES:0) won't cause a limit exception?
Whoops, now that you say it... 😖 You're right:P Looking at the protection code at that point (normal MMU address verification) had the limit check executed, but not applied (it calculated a variable which stores the boolean result of the comparision with the limit, then reverses(NOT) that when required with Expand-Down segments. But it never checked the resulting value and caused a #GP fault when it was 0.
Edit: I've disabled the limit check in real mode, as it seems the BIOS crashes with a #GP in real mode because of an incorrectly loaded limit during initialization for some reason.
Edit: Re-enabled it, but added proper segment descriptor initialization during reset operations(all segment registers but protected mode registers(LDTR and TR) as data segments).
Edit: It seem the modr/m 16-bit memory offset decoder wasn't wrapping it's addresses 100% correctly (correctly during the normal offset calculation, but incorrectly when applying extra offsets, like used in LDS and LES to load more than 8/16/32-bits of data in those specific sizes from memory). Now the BIOS boots correctly again, with segment limits enabled in both real and protected/V86 modes.
OK, the protected and real mode now properly use their respective segment limits and run. But for some reason, during that test, ES is loaded with a segment descriptor having a limit of 0xFFFF instead of 0x0000?
Edit: Now, the gathered information:
When loading the limit into the table, the DS descriptor that's cached contains 0x000093000000ffff. The offset used is 0x48. The calculated limit is 0xFFFF, so the access succeeds (together with the other checks). The zeroed out value is written to linear address 0x48. The high value(0x00) is written to offset 0x49. The rest of the values seem to be correctly written to the following addresses too.
Then it pushes selector 48h to the stack and POPs it into DS. DS is correctly loaded with selector 0x48. It loads the descriptor from the GDT, which is located at physical address 0xD8A0.
That's the cause of the invalid selector: the code assumes that DS points somewhere it doesn't? Why doesn't DS point to the correct location?
It's loaded at checkpoint F0 (after the SYSINIT1 CALL). So something's going wrong there?
Edit: It seems it loads the wrong descriptor for some reason? Maybe the GDT table is incorrectly set up?
Looking at the supposed entries for the GDT installed by the SYSINIT1 function, the DS descriptor should be loaded with segment value 0x08(The first entry in the GDT after the NULL descriptor). The entry at 0x48 (The 0x48 descriptor) should be the following descriptor, installed by the SYSINIT1's GDT_BLD subfunction:
1;----- TEMPORARY DESCRIPTOR FOR ES - (ES_TEMP) 2 3 DW MAX_SEG_LEN ; SEGMENT LIMIT 4 DW NSEG@_LO ; SEGMENT BASE ADDRESS - LOW WORD 5 DB NSEG@_HI ; SEGMENT BASE ADDRESS - HIGH BYTE 6 DB CPL0_DATA_ACCESS ; ACCESS RIGHTS BYTE 7 DW 0 ; RESERVED - MUST BE ZERO
Now the question is: is DS loaded with the correct descriptor? That doesn't seem so, looking at the source code.
Edit: DS seems to have been loaded with descriptor 08h. So it's the first descriptor in the GDT, but it contains an invalid descriptor for some reason?
Edit: The DS selector seems to load selector 08h(The GDT) correctly the first time it's used in protected mode. So that means the table is built correctly until it reaches checkpoint 0xF0. Maybe something goes wrong during initialization of the GDT during that step?
Edit: Something strange is happening: segmentWritten, which loads all segment descriptors, doesn't seem to be called for the MOV DS,AX; MOV ES,AX after protected mode is loaded at diagnostics code 0xF0+.
Edit: Debugging the instructions themselves, it seems that the instruction loads the value directly, not triggering any segment register updates when required. Thus the segment register was visibly loaded, but the descriptors weren't.
Edit: Implementing the fix by loading those segment registers correctly with the MOV instruction, at diagnostic code 0x1A, it tries to load SS with an invalid descriptor?
Edit: It seems to have caused an error because it was checking for the wrong bit (read-only SS isn't allowed). Having fixed this, the exception at diagnostics code 0xF2 is handled successfully 😀
Edit: Now an error seems to occur at step 0xF3, which crashes incorrectly.
Edit: After fixing the loading of the Task Register, it now moves on to the 0xF8 checks (LSL/LAR checks).
Edit: It now seems to check OK until it reaches the keyboard tests, after which it gives a keyboard locked error.
Edit: Fixing the keyboard locked error, it gets into an infinite loop? I can't make anything out of it, besides an infinite loop?
You are in manufacturing test mode, because a bit in keyboard controller port said so. It toggles 0x40 in a timer interrupt. I think it's a bit near the key inhibit.
Just tried running the old Turbo XT v2.5 BIOS on my current commit(80186/NEC V30 emulation): It screws up royally:( Something I did the last few weeks killed the XT emulation for some reason. Although I've mainly worked on the MMU and 80286(Besides various optimizations).
Unfortunately part of the code with my last release(see UniPCemu release thread) got lost during commiting(mainly VGA_Sequencer.c becoming VGA_Renderer.c, what's still known).
Is there a simple way to view all changes in a whole range of commits(from the point it still worked(at least weeks ago) in one single diff? Seeing as I want to keep most changes, as they're improvements and bugfixes, but remove the cause of the bug.
I remember it still working when I implemented the OSK, but the commit of the last release(which is permanently lost) already had the bug. So it was at least the release before that, where it was still working(IBM PC XT emulation).
After fixing the IBM PC XT emulation, the AT emulation now gives the following diagnostics:
100:00:03:26.00232: POST Code: 01 200:00:03:26.00644: POST Code: 02 300:00:03:43.02014: POST Code: 03 400:00:03:43.02150: POST Code: 04 500:00:03:43.02214: POST Code: 05 600:00:03:43.02287: POST Code: 06 700:00:03:43.02857: POST Code: 07 800:00:03:43.03445: POST Code: 08 900:00:03:43.03650: POST Code: 00 1000:00:03:43.03854: POST Code: 01 1100:00:03:43.04056: POST Code: 02 1200:00:03:43.04259: POST Code: 03 1300:00:03:43.04466: POST Code: 04 1400:00:03:43.04669: POST Code: 05 1500:00:03:43.04871: POST Code: 06 1600:00:03:43.05073: POST Code: 07 1700:00:03:43.05322: POST Code: 08 1800:00:03:43.05534: POST Code: 09 1900:00:03:43.05745: POST Code: 0A 2000:00:03:43.05974: POST Code: 0B 2100:00:03:43.06219: POST Code: 0C 2200:00:03:43.06435: POST Code: 0D 2300:00:03:43.06638: POST Code: 0E 2400:00:03:43.06861: POST Code: 0F 2500:00:03:43.07063: POST Code: 10 2600:00:03:43.07314: POST Code: 11 2700:00:03:43.07511: POST Code: 12 2800:00:03:43.07730: POST Code: 13 2900:00:03:43.07942: POST Code: 14 3000:00:03:43.08140: POST Code: 15 3100:00:03:43.08381: POST Code: 16 3200:00:03:43.08579: POST Code: 17 3300:00:03:43.08800: POST Code: 18 3400:00:03:43.09160: POST Code: 19 3500:00:03:43.09448: POST Code: 1A 3600:00:03:43.09720: POST Code: 1B 3700:00:03:43.09922: POST Code: 1C 3800:00:03:44.00124: POST Code: 1D 3900:00:03:44.00367: POST Code: 1E 4000:00:03:44.00579: POST Code: 1F 4100:00:03:44.00813: POST Code: 20 4200:00:03:44.01034: POST Code: 21 4300:00:03:44.01237: POST Code: 22 4400:00:03:44.01439: POST Code: 23 4500:00:03:44.01665: POST Code: 24 4600:00:03:44.01887: POST Code: 25 4700:00:03:44.02089: POST Code: 26 4800:00:03:44.02291: POST Code: 27 4900:00:03:44.02493: POST Code: 28 5000:00:03:44.02707: POST Code: 29 5100:00:03:44.02919: POST Code: 2A 5200:00:03:44.03121: POST Code: 2B 5300:00:03:44.03343: POST Code: 2C 5400:00:03:44.03544: POST Code: 2D 5500:00:03:44.03748: POST Code: 2E 5600:00:03:44.03949: POST Code: 2F 5700:00:03:44.04151: POST Code: 30 5800:00:03:44.04353: POST Code: 31 5900:00:03:44.04555: POST Code: 32 6000:00:03:44.04780: POST Code: 33
…Show last 790 lines
6100:00:03:44.05004: POST Code: 34 6200:00:03:44.05239: POST Code: 35 6300:00:03:44.05455: POST Code: 36 6400:00:03:44.05658: POST Code: 37 6500:00:03:44.05859: POST Code: 38 6600:00:03:44.06061: POST Code: 39 6700:00:03:44.06303: POST Code: 3A 6800:00:03:44.06505: POST Code: 3B 6900:00:03:44.06722: POST Code: 3C 7000:00:03:44.06924: POST Code: 3D 7100:00:03:44.07126: POST Code: 3E 7200:00:03:44.07328: POST Code: 3F 7300:00:03:44.07530: POST Code: 40 7400:00:03:44.07734: POST Code: 41 7500:00:03:44.07937: POST Code: 42 7600:00:03:44.08138: POST Code: 43 7700:00:03:44.08361: POST Code: 44 7800:00:03:44.08562: POST Code: 45 7900:00:03:44.08785: POST Code: 46 8000:00:03:44.09008: POST Code: 47 8100:00:03:44.09211: POST Code: 48 8200:00:03:44.09413: POST Code: 49 8300:00:03:44.09613: POST Code: 4A 8400:00:03:44.09840: POST Code: 4B 8500:00:03:45.00041: POST Code: 4C 8600:00:03:45.00244: POST Code: 4D 8700:00:03:45.00445: POST Code: 4E 8800:00:03:45.00647: POST Code: 4F 8900:00:03:45.00852: POST Code: 50 9000:00:03:45.01053: POST Code: 51 9100:00:03:45.01256: POST Code: 52 9200:00:03:45.01457: POST Code: 53 9300:00:03:45.01659: POST Code: 54 9400:00:03:45.01886: POST Code: 55 9500:00:03:45.02088: POST Code: 56 9600:00:03:45.02321: POST Code: 57 9700:00:03:45.02535: POST Code: 58 9800:00:03:45.07078: POST Code: 59 9900:00:03:45.07301: POST Code: 5A 10000:00:03:45.07499: POST Code: 5B 10100:00:03:45.07718: POST Code: 5C 10200:00:03:45.08133: POST Code: 5D 10300:00:03:45.08373: POST Code: 5E 10400:00:03:45.08570: POST Code: 5F 10500:00:03:45.08787: POST Code: 60 10600:00:03:45.08984: POST Code: 61 10700:00:03:45.09194: POST Code: 62 10800:00:03:45.09424: POST Code: 63 10900:00:03:45.09621: POST Code: 64 11000:00:03:45.09838: POST Code: 65 11100:00:03:46.00038: POST Code: 66 11200:00:03:46.00277: POST Code: 67 11300:00:03:46.00479: POST Code: 68 11400:00:03:46.00677: POST Code: 69 11500:00:03:46.00894: POST Code: 6A 11600:00:03:46.01093: POST Code: 6B 11700:00:03:46.01330: POST Code: 6C 11800:00:03:46.01527: POST Code: 6D 11900:00:03:46.01772: POST Code: 6E 12000:00:03:46.01969: POST Code: 6F 12100:00:03:46.02218: POST Code: 70 12200:00:03:46.02434: POST Code: 71 12300:00:03:46.02631: POST Code: 72 12400:00:03:46.02847: POST Code: 73 12500:00:03:46.03047: POST Code: 74 12600:00:03:46.03285: POST Code: 75 12700:00:03:46.03481: POST Code: 76 12800:00:03:46.03678: POST Code: 77 12900:00:03:46.03895: POST Code: 78 13000:00:03:46.04098: POST Code: 79 13100:00:03:46.04315: POST Code: 7A 13200:00:03:46.04514: POST Code: 7B 13300:00:03:46.04744: POST Code: 7C 13400:00:03:46.04950: POST Code: 7D 13500:00:03:46.05149: POST Code: 7E 13600:00:03:46.05366: POST Code: 7F 13700:00:03:46.05576: POST Code: 80 13800:00:03:46.05793: POST Code: 81 13900:00:03:46.05990: POST Code: 82 14000:00:03:46.06276: POST Code: 83 14100:00:03:46.06473: POST Code: 84 14200:00:03:46.06669: POST Code: 85 14300:00:03:46.06887: POST Code: 86 14400:00:03:46.07086: POST Code: 87 14500:00:03:46.07329: POST Code: 88 14600:00:03:46.07526: POST Code: 89 14700:00:03:46.07744: POST Code: 8A 14800:00:03:46.07942: POST Code: 8B 14900:00:03:46.08140: POST Code: 8C 15000:00:03:46.08384: POST Code: 8D 15100:00:03:46.08582: POST Code: 8E 15200:00:03:46.08799: POST Code: 8F 15300:00:03:46.08996: POST Code: 90 15400:00:03:46.09206: POST Code: 91 15500:00:03:46.09412: POST Code: 92 15600:00:03:46.09609: POST Code: 93 15700:00:03:46.09846: POST Code: 94 15800:00:03:47.00043: POST Code: 95 15900:00:03:47.00263: POST Code: 96 16000:00:03:47.00460: POST Code: 97 16100:00:03:47.00657: POST Code: 98 16200:00:03:47.00910: POST Code: 99 16300:00:03:47.01124: POST Code: 9A 16400:00:03:47.01342: POST Code: 9B 16500:00:03:47.01539: POST Code: 9C 16600:00:03:47.01779: POST Code: 9D 16700:00:03:47.01996: POST Code: 9E 16800:00:03:47.02219: POST Code: 9F 16900:00:03:47.02500: POST Code: A0 17000:00:03:47.02727: POST Code: A1 17100:00:03:47.02929: POST Code: A2 17200:00:03:47.03134: POST Code: A3 17300:00:03:47.03357: POST Code: A4 17400:00:03:47.03558: POST Code: A5 17500:00:03:47.03781: POST Code: A6 17600:00:03:47.03983: POST Code: A7 17700:00:03:47.04198: POST Code: A8 17800:00:03:47.04409: POST Code: A9 17900:00:03:47.04610: POST Code: AA 18000:00:03:47.04833: POST Code: AB 18100:00:03:47.05035: POST Code: AC 18200:00:03:47.05258: POST Code: AD 18300:00:03:47.05460: POST Code: AE 18400:00:03:47.05661: POST Code: AF 18500:00:03:47.05884: POST Code: B0 18600:00:03:47.06086: POST Code: B1 18700:00:03:47.06309: POST Code: B2 18800:00:03:47.06511: POST Code: B3 18900:00:03:47.06746: POST Code: B4 19000:00:03:47.06948: POST Code: B5 19100:00:03:47.07151: POST Code: B6 19200:00:03:47.07354: POST Code: B7 19300:00:03:47.07555: POST Code: B8 19400:00:03:47.07758: POST Code: B9 19500:00:03:47.07959: POST Code: BA 19600:00:03:47.08162: POST Code: BB 19700:00:03:47.08384: POST Code: BC 19800:00:03:47.08586: POST Code: BD 19900:00:03:47.08789: POST Code: BE 20000:00:03:47.08990: POST Code: BF 20100:00:03:47.09205: POST Code: C0 20200:00:03:47.09417: POST Code: C1 20300:00:03:47.09618: POST Code: C2 20400:00:03:47.09821: POST Code: C3 20500:00:03:48.00023: POST Code: C4 20600:00:03:48.00249: POST Code: C5 20700:00:03:48.00450: POST Code: C6 20800:00:03:48.00652: POST Code: C7 20900:00:03:48.00875: POST Code: C8 21000:00:03:48.01076: POST Code: C9 21100:00:03:48.01280: POST Code: CA 21200:00:03:48.01482: POST Code: CB 21300:00:03:48.01700: POST Code: CC 21400:00:03:48.01922: POST Code: CD 21500:00:03:48.02133: POST Code: CE 21600:00:03:48.02369: POST Code: CF 21700:00:03:48.02585: POST Code: D0 21800:00:03:48.02793: POST Code: D1 21900:00:03:48.03006: POST Code: D2 22000:00:03:48.03230: POST Code: D3 22100:00:03:48.03431: POST Code: D4 22200:00:03:48.03644: POST Code: D5 22300:00:03:48.03880: POST Code: D6 22400:00:03:48.04077: POST Code: D7 22500:00:03:48.04277: POST Code: D8 22600:00:03:48.04475: POST Code: D9 22700:00:03:48.04672: POST Code: DA 22800:00:03:48.04911: POST Code: DB 22900:00:03:48.05129: POST Code: DC 23000:00:03:48.05369: POST Code: DD 23100:00:03:48.05599: POST Code: DE 23200:00:03:48.05802: POST Code: DF 23300:00:03:48.06004: POST Code: E0 23400:00:03:49.00706: POST Code: E1 23500:00:03:49.00923: POST Code: E2 23600:00:03:49.01127: POST Code: E3 23700:00:03:49.01361: POST Code: E4 23800:00:03:49.01568: POST Code: E5 23900:00:03:49.01805: POST Code: E6 24000:00:03:49.02009: POST Code: E7 24100:00:03:49.02238: POST Code: E8 24200:00:03:49.02445: POST Code: E9 24300:00:03:49.02657: POST Code: EA 24400:00:03:49.02889: POST Code: EB 24500:00:03:49.03120: POST Code: EC 24600:00:03:49.03347: POST Code: ED 24700:00:03:49.03596: POST Code: EE 24800:00:03:49.03906: POST Code: EF 24900:00:03:49.04111: POST Code: F0 25000:00:03:49.04345: POST Code: F1 25100:00:03:49.04554: POST Code: F2 25200:00:03:49.04797: POST Code: F3 25300:00:03:49.04995: POST Code: F4 25400:00:03:49.05203: POST Code: F5 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75000:04:19:75.08512: POST Code: B2 75100:04:19:75.08720: POST Code: B3 75200:04:19:75.08928: POST Code: B4 75300:04:19:75.09216: POST Code: B5 75400:04:19:75.09488: POST Code: B6 75500:04:19:75.09808: POST Code: B7 75600:04:19:76.00112: POST Code: B8 75700:04:19:76.00416: POST Code: B9 75800:04:19:76.00720: POST Code: BA 75900:04:19:76.01008: POST Code: BB 76000:04:19:76.01328: POST Code: BC 76100:04:19:76.01616: POST Code: BD 76200:04:19:76.01920: POST Code: BE 76300:04:19:76.02192: POST Code: BF 76400:04:19:76.02512: POST Code: C0 76500:04:19:76.02848: POST Code: C1 76600:04:19:76.03136: POST Code: C2 76700:04:19:76.03424: POST Code: C3 76800:04:19:76.03712: POST Code: C4 76900:04:19:76.04016: POST Code: C5 77000:04:19:76.04304: POST Code: C6 77100:04:19:76.04576: POST Code: C7 77200:04:19:76.04880: POST Code: C8 77300:04:19:76.05152: POST Code: C9 77400:04:19:76.05456: POST Code: CA 77500:04:19:76.05744: POST Code: CB 77600:04:19:76.06032: POST Code: CC 77700:04:19:76.06320: POST Code: CD 77800:04:19:76.06592: POST Code: CE 77900:04:19:76.06912: POST Code: CF 78000:04:19:76.07184: POST Code: D0 78100:04:19:76.07680: POST Code: D1 78200:04:19:76.08016: POST Code: D2 78300:04:19:76.08320: POST Code: D3 78400:04:19:76.08592: POST Code: D4 78500:04:19:76.08912: POST Code: D5 78600:04:19:76.09264: POST Code: D6 78700:04:19:76.09600: POST Code: D7 78800:04:19:77.00000: POST Code: D8 78900:04:19:77.00320: POST Code: D9 79000:04:19:77.00688: POST Code: DA 79100:04:19:77.01024: POST Code: DB 79200:04:19:77.01296: POST Code: DC 79300:04:19:77.01616: POST Code: DD 79400:04:19:77.01936: POST Code: DE 79500:04:19:77.02224: POST Code: DF 79600:04:19:77.02512: POST Code: E0 79700:04:19:77.02848: POST Code: E1 79800:04:19:77.03184: POST Code: E2 79900:04:19:77.03616: POST Code: E3 80000:04:19:77.03936: POST Code: E4 80100:04:19:77.04224: POST Code: E5 80200:04:19:77.04512: POST Code: E6 80300:04:19:77.04784: POST Code: E7 80400:04:19:77.05072: POST Code: E8 80500:04:19:77.05392: POST Code: E9 80600:04:19:77.05680: POST Code: EA 80700:04:19:77.05968: POST Code: EB 80800:04:19:77.06176: POST Code: EC 80900:04:19:77.06464: POST Code: ED 81000:04:19:77.06672: POST Code: EE 81100:04:19:77.06864: POST Code: EF 81200:04:19:77.07088: POST Code: F0 81300:04:19:77.07328: POST Code: F1 81400:04:19:77.07568: POST Code: F2 81500:04:19:77.07856: POST Code: F3 81600:04:19:77.08144: POST Code: F4 81700:04:19:77.08432: POST Code: F5 81800:04:19:77.08720: POST Code: F6 81900:04:19:77.09056: POST Code: F7 82000:04:19:77.09328: POST Code: F8 82100:04:19:77.09616: POST Code: F9 82200:04:19:77.09920: POST Code: FA 82300:04:19:78.00208: POST Code: FB 82400:04:19:78.00528: POST Code: FC 82500:04:19:78.00816: POST Code: FD 82600:04:19:78.01168: POST Code: 09 82700:04:19:78.01216: POST Code: 0A 82800:04:19:78.01232: POST Code: 0B 82900:04:19:78.01280: POST Code: 0C 83000:04:19:78.01344: POST Code: 0E 83100:04:19:78.01376: POST Code: 0F 83200:04:21:47.04096: POST Code: 32 83300:04:21:90.09168: POST Code: 11 83400:04:21:91.08336: POST Code: 12 83500:04:21:91.08720: POST Code: 13 83600:04:21:91.08768: POST Code: 14 83700:04:21:92.05200: POST Code: 15 83800:04:21:92.05360: POST Code: 16 83900:04:21:92.05456: POST Code: 17 84000:04:21:92.05568: POST Code: 18 84100:04:21:92.05584: POST Code: 19 84200:04:21:92.05648: POST Code: 81 84300:04:21:93.00832: POST Code: 85 84400:04:21:93.00848: POST Code: 1A 84500:04:21:93.00896: POST Code: 1B 84600:04:25:17.00768: POST Code: 1C 84700:04:25:17.00896: POST Code: 1D 84800:04:25:33.04448: POST Code: 21 84900:04:25:58.03552: POST Code: 23
I see it's arriving to code 40h, which is the Math Coprocessor test?
Edit: It seems the Math Coprocessor isn't detected (which is the case, as it's not emulated(it has dummy handlers for ET and EM emulation, while actual instructions given to it result in no effect at all without software emulation or exceptions because the task is switched. They're effectively NOP instructions with unused modr/m parameters if that's the case).
After that, it seems to detect some 'manufacturing burn-in test':
1F15A_0: 2 TEST @MFG_TST,MFG_LOOP ; MFG BURN IN MODE 3 JNZ F15A ; GO IF NOT 4 JMP START_1 ; GO LOOP POST 5F15A: CMP BYTE PTR @RESET_FLAG,64H ; MFG RUN IN? 6 JZ F15B ; BYPASS BEEP IF YES
This data is apparently gotten from the 8042 controller?
1;----- GET THE SWITCH SETTINGS 2 MOV AL,READ_8042_INPUT ; READ INPUT COMMAND 3 MOV SP:OFFSET C8042C ; SET RETURN ADDRESS 4 JMP SHORT C8042 ; ISSUE COMMAND 5E30B: MOV SP,OFFSET OBF_42B ; SET RETURN ADDRESS 6 JMP SHORT OBF_42 ; GO WAIT FOR RESPONSE 7E30C: IN AL,PORT_A ; GET THE SWITCH 8 OUT DMA_PAGE+1,AL ; SAVE TEMPORARY
So there's already a problem at point 0Ch?
Edit: Having implemented the proper input port emulation (bits 7 and 4 are always set. Bit 6 is being set with MDA emulation, cleared with CGA/(S)VGA emulation).
It now tries to read the floppy (I see it's enabling the drive motor(s)). It finally gives two errors:
106144 KB OK 2301-Keyboard Error 3161-System Options Not Set-(Run SETUP) 4 5(RESUME = "F1" KEY)
This is my current log (With the same last output of the previous post):
100:00:07:04.05271: POST Code: 01 200:00:07:04.05996: POST Code: 02 300:00:07:21.08713: POST Code: 03 400:00:07:21.08860: POST Code: 04 500:00:07:21.08929: POST Code: 05 600:00:07:21.08989: POST Code: 06 700:00:07:21.09490: POST Code: 07 800:00:07:22.00077: POST Code: 08 900:00:07:22.00274: POST Code: 00 1000:00:07:22.00492: POST Code: 01 1100:00:07:22.00687: POST Code: 02 1200:00:07:22.00884: POST Code: 03 1300:00:07:22.01078: POST Code: 04 1400:00:07:22.01274: POST Code: 05 1500:00:07:22.01541: POST Code: 06 1600:00:07:22.01737: POST Code: 07 1700:00:07:22.06115: POST Code: 08 1800:00:07:22.06333: POST Code: 09 1900:00:07:22.06538: POST Code: 0A 2000:00:07:22.06734: POST Code: 0B 2100:00:07:22.06963: POST Code: 0C 2200:00:07:22.07164: POST Code: 0D 2300:00:07:22.07358: POST Code: 0E 2400:00:07:22.07556: POST Code: 0F 2500:00:07:22.07751: POST Code: 10 2600:00:07:22.07977: POST Code: 11 2700:00:07:22.08173: POST Code: 12 2800:00:07:22.08368: POST Code: 13 2900:00:07:22.08577: POST Code: 14 3000:00:07:22.08772: POST Code: 15 3100:00:07:22.08992: POST Code: 16 3200:00:07:22.09243: POST Code: 17 3300:00:07:22.09573: POST Code: 18 3400:00:07:22.09999: POST Code: 19 3500:00:07:23.00270: POST Code: 1A 3600:00:07:23.00520: POST Code: 1B 3700:00:07:23.00714: POST Code: 1C 3800:00:07:23.00911: POST Code: 1D 3900:00:07:23.01107: POST Code: 1E 4000:00:07:23.01321: POST Code: 1F 4100:00:07:23.01646: POST Code: 20 4200:00:07:23.01990: POST Code: 21 4300:00:07:23.02316: POST Code: 22 4400:00:07:23.02649: POST Code: 23 4500:00:07:23.03064: POST Code: 24 4600:00:07:23.03471: POST Code: 25 4700:00:07:23.03806: POST Code: 26 4800:00:07:23.04193: POST Code: 27 4900:00:07:23.04607: POST Code: 28 5000:00:07:23.05053: POST Code: 29 5100:00:07:23.05272: POST Code: 2A 5200:00:07:23.05481: POST Code: 2B 5300:00:07:23.05686: POST Code: 2C 5400:00:07:23.05895: POST Code: 2D 5500:00:07:23.06117: POST Code: 2E 5600:00:07:23.06328: POST Code: 2F 5700:00:07:23.06529: POST Code: 30 5800:00:07:23.06729: POST Code: 31 5900:00:07:23.06930: POST Code: 32 6000:00:07:23.07131: POST Code: 33
…Show last 463 lines
6100:00:07:23.07331: POST Code: 34 6200:00:07:23.07562: POST Code: 35 6300:00:07:23.07761: POST Code: 36 6400:00:07:23.07962: POST Code: 37 6500:00:07:23.08164: POST Code: 38 6600:00:07:23.08362: POST Code: 39 6700:00:07:23.08566: POST Code: 3A 6800:00:07:23.08765: POST Code: 3B 6900:00:07:23.08967: POST Code: 3C 7000:00:07:23.09167: POST Code: 3D 7100:00:07:23.09366: POST Code: 3E 7200:00:07:23.09568: POST Code: 3F 7300:00:07:23.09767: POST Code: 40 7400:00:07:23.09969: POST Code: 41 7500:00:07:24.00170: POST Code: 42 7600:00:07:24.00369: POST Code: 43 7700:00:07:24.00570: POST Code: 44 7800:00:07:24.00769: POST Code: 45 7900:00:07:24.01005: POST Code: 46 8000:00:07:24.01206: POST Code: 47 8100:00:07:24.01407: POST Code: 48 8200:00:07:24.01606: POST Code: 49 8300:00:07:24.01805: POST Code: 4A 8400:00:07:24.02030: POST Code: 4B 8500:00:07:24.02271: POST Code: 4C 8600:00:07:24.02480: POST Code: 4D 8700:00:07:24.02679: POST Code: 4E 8800:00:07:24.02881: POST Code: 4F 8900:00:07:24.03080: POST Code: 50 9000:00:07:24.03287: POST Code: 51 9100:00:07:24.03484: POST Code: 52 9200:00:07:24.03678: POST Code: 53 9300:00:07:24.03874: POST Code: 54 9400:00:07:24.04100: POST Code: 55 9500:00:07:24.04297: POST Code: 56 9600:00:07:24.04494: POST Code: 57 9700:00:07:24.04689: POST Code: 58 9800:00:07:24.04902: POST Code: 59 9900:00:07:24.05097: POST Code: 5A 10000:00:07:24.05293: POST Code: 5B 10100:00:07:24.05522: POST Code: 5C 10200:00:07:24.05717: POST Code: 5D 10300:00:07:24.05913: POST Code: 5E 10400:00:07:24.06108: POST Code: 5F 10500:00:07:24.06304: POST Code: 60 10600:00:07:24.06500: POST Code: 61 10700:00:07:24.06695: POST Code: 62 10800:00:07:24.06913: POST Code: 63 10900:00:07:24.07127: POST Code: 64 11000:00:07:24.07323: POST Code: 65 11100:00:07:24.07520: POST Code: 66 11200:00:07:24.07715: POST Code: 67 11300:00:07:24.07911: POST Code: 68 11400:00:07:24.08106: POST Code: 69 11500:00:07:24.08302: POST Code: 6A 11600:00:07:24.08542: POST Code: 6B 11700:00:07:24.08738: POST Code: 6C 11800:00:07:24.08933: POST Code: 6D 11900:00:07:24.09127: POST Code: 6E 12000:00:07:24.09323: POST Code: 6F 12100:00:07:24.09521: POST Code: 70 12200:00:07:24.09716: POST Code: 71 12300:00:07:24.09942: POST Code: 72 12400:00:07:25.00136: POST Code: 73 12500:00:07:25.00332: POST Code: 74 12600:00:07:25.00529: POST Code: 75 12700:00:07:25.00723: POST Code: 76 12800:00:07:25.00919: POST Code: 77 12900:00:07:25.01114: POST Code: 78 13000:00:07:25.01311: POST Code: 79 13100:00:07:25.01546: POST Code: 7A 13200:00:07:25.01740: POST Code: 7B 13300:00:07:25.01938: POST Code: 7C 13400:00:07:25.02133: POST Code: 7D 13500:00:07:25.02329: POST Code: 7E 13600:00:07:25.02530: POST Code: 7F 13700:00:07:25.02739: POST Code: 80 13800:00:07:25.02964: POST Code: 81 13900:00:07:25.03159: POST Code: 82 14000:00:07:25.03355: POST Code: 83 14100:00:07:25.03551: POST Code: 84 14200:00:07:25.03746: POST Code: 85 14300:00:07:25.03943: POST Code: 86 14400:00:07:25.04137: POST Code: 87 14500:00:07:25.04336: POST Code: 88 14600:00:07:25.04560: POST Code: 89 14700:00:07:25.04755: POST Code: 8A 14800:00:07:25.04951: POST Code: 8B 14900:00:07:25.05146: POST Code: 8C 15000:00:07:25.09495: POST Code: 8D 15100:00:07:25.09711: POST Code: 8E 15200:00:07:25.09922: POST Code: 8F 15300:00:07:26.00116: POST Code: 90 15400:00:07:26.00311: POST Code: 91 15500:00:07:26.00541: POST Code: 92 15600:00:07:26.00736: POST Code: 93 15700:00:07:26.00932: POST Code: 94 15800:00:07:26.01126: POST Code: 95 15900:00:07:26.01321: POST Code: 96 16000:00:07:26.01580: POST Code: 97 16100:00:07:26.01820: POST Code: 98 16200:00:07:26.02062: POST Code: 99 16300:00:07:26.02257: POST Code: 9A 16400:00:07:26.02498: POST Code: 9B 16500:00:07:26.02693: POST Code: 9C 16600:00:07:26.02890: POST Code: 9D 16700:00:07:26.03085: POST Code: 9E 16800:00:07:26.03300: POST Code: 9F 16900:00:07:26.03539: POST Code: A0 17000:00:07:26.03735: POST Code: A1 17100:00:07:26.03931: POST Code: A2 17200:00:07:26.04127: POST Code: A3 17300:00:07:26.04323: POST Code: A4 17400:00:07:26.04528: POST Code: A5 17500:00:07:26.04729: POST Code: A6 17600:00:07:26.05097: POST Code: A7 17700:00:07:26.05320: POST Code: A8 17800:00:07:26.05572: POST Code: A9 17900:00:07:26.05782: POST Code: AA 18000:00:07:26.06003: POST Code: AB 18100:00:07:26.06202: POST Code: AC 18200:00:07:26.06402: POST Code: AD 18300:00:07:26.06607: POST Code: AE 18400:00:07:26.06802: POST Code: AF 18500:00:07:26.07037: POST Code: B0 18600:00:07:26.07238: POST Code: B1 18700:00:07:26.07434: POST Code: B2 18800:00:07:26.07629: POST Code: B3 18900:00:07:26.07824: POST Code: B4 19000:00:07:26.08018: POST Code: B5 19100:00:07:26.08213: POST Code: B6 19200:00:07:26.08430: POST Code: B7 19300:00:07:26.08646: POST Code: B8 19400:00:07:26.08840: POST Code: B9 19500:00:07:26.09055: POST Code: BA 19600:00:07:26.09249: POST Code: BB 19700:00:07:26.09445: POST Code: BC 19800:00:07:26.09641: POST Code: BD 19900:00:07:26.09836: POST Code: BE 20000:00:07:27.00072: POST Code: BF 20100:00:07:27.00266: POST Code: C0 20200:00:07:27.00461: POST Code: C1 20300:00:07:27.00657: POST Code: C2 20400:00:07:27.00852: POST Code: C3 20500:00:07:27.01152: POST Code: C4 20600:00:07:27.01371: POST Code: C5 20700:00:07:27.01620: POST Code: C6 20800:00:07:27.01814: POST Code: C7 20900:00:07:27.02059: POST Code: C8 21000:00:07:27.02295: POST Code: C9 21100:00:07:27.02537: POST Code: CA 21200:00:07:27.02785: POST Code: CB 21300:00:07:27.02995: POST Code: CC 21400:00:07:27.03194: POST Code: CD 21500:00:07:27.03405: POST Code: CE 21600:00:07:27.03617: POST Code: CF 21700:00:07:27.03816: POST Code: D0 21800:00:07:27.04045: POST Code: D1 21900:00:07:27.04240: POST Code: D2 22000:00:07:27.04435: POST Code: D3 22100:00:07:27.04633: POST Code: D4 22200:00:07:27.04828: POST Code: D5 22300:00:07:27.05076: POST Code: D6 22400:00:07:27.05283: POST Code: D7 22500:00:07:27.05543: POST Code: D8 22600:00:07:27.05835: POST Code: D9 22700:00:07:27.06142: POST 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superfury wrote:It finally gives two errors: […] Show full quote
It finally gives two errors:
106144 KB OK 2301-Keyboard Error 3161-System Options Not Set-(Run SETUP) 4 5(RESUME = "F1" KEY)
The keyboard error could be because you are only emulating an XT style interface? The AT had a bidirectional keyboard bus, and probably sends some diagnostics stuff to the keyboard, and expects something in return which it isn't getting.
The system options not set is probably because it expects something specific in the CMOS bytes of the MC146818 chip (where the configuration is stored for an AT).
If you emulate that chip, you should indeed be able to run the setup utility, set it up once, and then reboot it without this error (this is non-volatile ram, so your emulator will have to save this data somewhere, so it is preserved between reboots or even different sessions of running the emulator).
See here for more info, it's port 0x70 and 0x71 to access the CMOS registers/storage: http://wiki.osdev.org/CMOS#Accessing_CMOS_Registers
Here's a map of what the storage is used for: http://www.bioscentral.com/misc/cmosmap.htm
I'm seeing something strange when debugging through the keyboard test of the AT BIOS:
1;------------------------------------------------ 2;TEST.21 : 3; KEYBOARD TEST : 4; DESCRIPTION : 5; RESET THE KEYBOARD AND CHECK THAT SCAN : 6; CODE *AA" IS RETURNED TO THE PROCESSOR. : 7; CHECK FOR STUCK KEYS. : 8;------------------------------------------------ 9 10 MOV AL,35H ; <><><><><><><><><><><><> 11 OUT MFG_PORT,AL ; <><> CHECKPOINT 35 <><>
That block eventually will try to reset the keyboard, but when it reaches the following line:
1 CMP BL,KB_OK ; SCAN CODE AS EXPECTED? 2 JNE F6 ; NO - DISPLAY ERROR MESSAGE 3 4;----- CHECK FOR STUCK KEYS
0xAA(The self test passed result) is in AL instead of BL?
The full code is:
1;------------------------------------------------ 2;TEST.21 : 3; KEYBOARD TEST : 4; DESCRIPTION : 5; RESET THE KEYBOARD AND CHECK THAT SCAN : 6; CODE *AA" IS RETURNED TO THE PROCESSOR. : 7; CHECK FOR STUCK KEYS. : 8;------------------------------------------------ 9 10 MOV AL,35H ; <><><><><><><><><><><><> 11 OUT MFG_PORT,AL ; <><> CHECKPOINT 35 <><> 12 13 TEST @MFG_TST,MFG_LOOP ; MANUFACTURING BURN IN TEST MODE? 14 JNZ F7_A 15 JMP F7 ; YES - SKIP KEYBOARD TEST 16F7_A: CMP BYTE PTR @RESET_FLAG,064H ; MANUFACTURING RUN IN MODE? 17 JNZ F7_B 18 JMP F7 ; YES - SKIP KEYBOARD TEST 19F7_B: MOV AL,36H ; <><><><><><><><><><><><> 20 OUT MFG_PORT,AL ; <><> CHECKPOINT 36 <><> 21 CLI 22 CMP @RESET_FLAG,1234H ; SOFT RESET? 23 JZ G10 24 CMP BYTE PTR @RESET_FLAG,KB_OK ; CHECK FOR AA ALREADY RECEIVED 25 JZ G10 ; GO IF YES 26 MOV AL,ENA_KBD 27 CALL C8042 ; ENABLE KEYBOARD 28 MOV BH,4 ; TRY 4 TIMES 29LOOP1: CALL OBF_42 ; CHECK FOR OUTPUT BUFFER FULL 30 JNZ G10 ; GO IF BUFFER FULL 31 DEC BH 32 JNZ LOOP1 33G10: MOV AL,DIS_KBD ; DISABLE KEYBOARD 34 CALL C8042 35 IN AL,PORT_A ; FLUSH 36 MOV AL,KYBD_CLK_DATA ; GET THE CLOCK AND DATA LINES 37 CALL C8042 38 CALL OBF_42 ; WAIT FOR OUTPUT BUFFER FULL 39 IN AL,PORT_A ; GET THE RESULTS 40 TEST AL,KYBD_CLK ; KEYBOARD CLOCK MUST BE LOW 41 JZ G11 42 43 OR @MFG_ERR_FLAG+1,KYCLK_FAIL ; <><><><><><><><><><><><><><><> 44 ; <><> KEYBOARD CLOCK HIGH <><> 45 MOV SI,OFFSET E304 ; DISPLAY 304 ERROR 46 JMP SHORT F6D ; REPORT ERROR 47G11: CALL KBD_RESET ; ISSUE RESET TO KEYBOARD 48 JCXZ F6 ; PRINT ERROR MESSAGE IF NO INTERRUPT 49 MOV AL,37H ; <><><><><><><><><><><><> 50 OUT MFG_PORT,AL ; <><> CHECKPOINT 37 <><> 51 CMP BL,KB_OK ; SCAN CODE AS EXPECTED? 52 JNE F6 ; NO - DISPLAY ERROR MESSAGE
My reset function in the PS/2 keyboard controller:
1 case 0xFF: //Reset? 2 input_lastwrite_keyboard(); //Clear buffer for our result! 3 give_keyboard_input(0xFA); //Acnowledge! 4 input_lastwrite_keyboard(); //Force 0xFA to user! 5 resetKeyboard(1); //Reset the Keyboard Controller! 6 Keyboard.has_command = 0; //No command anymore! 7 break;
resetKeyboard also adds the 0xAA byte to the keyboard output buffer.
Btw the 8042 and PS/2 keyboard have a dual function: They support both 8042 PS/2 style and IBM XT style keyboards. The main difference is that the IBM AT automatically acnowledges the read data, while the XT disables the PS/2 mouse and requires bit 1 of port 0x61 to be raise(low-to-high transition) to clear the 8042 output buffer.
Is this correct?
Last edited by superfury on 2016-09-21, 13:53. Edited 1 time in total.
0xAA(The self test passed result) is in AL instead of BL?
It should be in BL.
As you can see, it calls KBD_RESET. This reads from the keyboard, and copies AL to BL before it returns.
So the last byte read by KBD_RESET should be in BL at that point.
That is of course assuming that CX was not zero when KBD_RESET returned, because that would mean there was an error.
So I would check what happens in KBD_RESET... Does it successfully reset the keyboard and actually read the byte there?
Edit: Thinking about it: this might actually be the very first BAT completed code, which is sent when the emulator itself starts. Once the keyboard port (8042 port 0) is enabled, it immediately receives this byte. Then, with 0xAA in the output buffer, the BIOS sends a 0xFF command to reset the PS/2 keyboard. This command adds 0xFA and then 0xAA to the PS/2 keyboard output buffer(data ready to be sent to the 8042 once it's output buffer is read(and cleared). The BIOS then reads the BAT code that's from the PS/2 keyboard when it's initialized by the emulator itself. The 8042 then reads the 0xFA byte from the PS/2 controller, but it's too late: the BIOS already has read and compared the emulator initialized BAT result code and compares it to 0xFA, which fails and makes the BIOS think the PS/2 keyboard is corrupt, giving the incorrect 0xAA result in AL and aborting the function with an error.
Is it correct that the PS/2 keyboard starts with 0xAA in it's output buffer when the PC is powered on(while the BIOS is still checking basic hardware, not even looking at PS/2 devices yet?
Btw the 8042 and PS/2 keyboard have a dual function: They support both 8042 PS/2 style and IBM XT style keyboards. The main difference is that the IBM AT automatically acnowledges the read data, while the XT disables the PS/2 mouse and requires bit 1 of port 0x61 to be raise(low-to-high transition) to clear the 8042 output buffer.
Is this correct?
Not really. The PS/2 mouse is not also relevant here.
XT and AT keyboards send different protocol on wires, they have different amount of bits.
They also send different scancode data, but on AT the 8042 will convert scancodes so that port 60h contains XT compatible scancodes.
On XT, the hardware will jam the clock so keyboard can't send more, and thus requires the 0x80 bit flipping to free the bus. Yes on AT the 8042 will handle everything.
The routine still gives the same error, even though the output buffer of the Keyboard should be empty (and nothing is received yet when the routine should start). I've disabled the initial 0xAA put in the keyboard's output buffer when the emulator starts. So when it gets to the keyboard routine, the 8042 can't receive anything until the 0xFF command is sent. That should make it fill it's buffers with the 0xFA and then the 0xAA bytes from the PS/2 keyboard?
Why are we even talking about PS/2?
An AT is a completely different machine, and predates the PS/2 by a number of years.
You're trying to run an AT BIOS on a 286 emulator. PS/2 doesn't enter the equation.
Edit: Does this mean there's a problem with the 8042 microcontroller itself?
Edit: Just implemented the 8042 disable/enable port bits to prevent input from the mouse and keyboard on power-up and when disabled through the configuration byte and enable/disable commands. I've also restored the PS/2 keyboard's BAT sending when emulation is started.
Since the port is disabled until the 0xFF reset command is sent, the 0xAA byte should be removed by the reset command? Thus proper results(as well as the PS/2 Mouse not sending any, since it stays disabled.
Because the IBM AT has a 8042 controller, which connects to a PS/2 Keyboard (and Mouse on the second port)?
PS/2 keyboards and mice weren't even invented until years later.
The AT is from 1984, PS/2 is from 1987.
The AT didn't have a mouse port. Back then people still used serial mice, if they used a mouse at all, or they used a specific 'bus mouse' with ISA card.
They may both use the same controller chip, but the AT doesn't use it exactly the same way as the PS/2 does. Some status/control bits are different on PS/2 because of the extra mouse port.
I also believe that PS/2 keyboards support some additional commands.
Anyway, don't worry about PS/2.
So I essentially just disable all PS/2 mouse and PS/2 keyboard commands and disable the second PS/2 port (and specific bits) permanently for full IBM PC AT compatibility?
Edit: I've just modified the 8042, PS/2 keyboard and PS/2 mouse to start disabled when used. The PS/2 keyboard is now enabled on the first write to it(through port 0x60).
Unfortunately I don't know the differences between a PS/2 Keyboard and AT keyboard(and/or 8042), so I don't know which commands are AT and which ones PS/2, so I can't disable the PS/2 commands.
Using that, I can modify and fix the 8042 itself, but I still don't know anything about the 8042 keyboard controller?
Edit: Just implemented 8042 scancode set 'translation', 'Bochs-style' (simply force the scancode set of the keys sent to scancode set 1 when enabled). Sending data to any device (PS/2 mouse or keyboard) now enables the corresponding device(see os2museum article).
The BIOS still errors our for some reason? If I remember the Assembler code correctly, the initial 0xAA byte should have been discarded when enabling the keyboard for the first time?
The keyboard itself reports it's ID as 0xAB, 0x83. Is this correct for the AT keyboard?
Looking at the code and debugging each step with the emulator debugger:
1;------------------------------------------------------------------ 2; THIS SUBROUTINE SENDS AN OUTPUT COMMAND TO THE KEYBOARD AND : 3; RECEIVES THE KEYBOARD RESPONSE. : 4; ENTRY REQUIREMENTS: : 5; AL = COMMAND/DATA TO BE SENT : 6; EXIT PARAMETERS: : 7; ZERO FLAG = 1 IF ACK RECEIVED FROM THE KEY BOARD : 8; AL = RESPONSE : 9;------------------------------------------------------------------ 10 11XMIT_8042 PROC NEAR 12 13;----- CHECK INPUT BUFFER FULL 14 15 XCHG AH,AL ; SAVE COMMAND 16 SUB CX,CX ; SET LOOP TIME-OUT 17XMITLOOP: 18 IN AL,STATUS_PORT 19 TEST AL,INPT_BUF_FULL ; CHECK INPUT BUFFER FULL 20 LOOPNZ XMITLOOP 21 JCXZ SHORT XMIT_EXIT 22 XCHG AH,AL ; RESTORE COMMAND 23 24;----- ISSUE THE COMMAND 25 26 OUT PORT_A,AL ; SEND THE COMMAND 27 SUB CX,CX ; SET LOOP COUNT 28 29;----- CHECK OUTPUT BUFFER FULL 30 31XMIT_1: IN AL,STATUS_PORT 32 MOV AH,AL ; SAVE STATUS 33 TEST AL,OUT_BUF_FULL ; CHECK IF 8042 HAS DATA 34 JZ XMIT_2 ; GO IF NOT 35 IN AL,PORT_A ; FLUSH DATA 36XMIT_2: TEST AH,INPT_BUF_FULL ; CHECK COMMAND ACCEPTED 37 LOOPNZ XMIT_1 38 JNZ SHORT XMIT_EXIT ; NO FLUSH OR COMMAND NOT ACCEPTED 39 40;----- CHECK OUTPUT BUFFER FULL 41 42 MOV BL,6 ; SET COUNT 43 SUB CX,CX ; SET LOOP COUNT 44XMIT_3: IN AL,STATUS_PORT 45 TEST AL,OUT_BUF_PULL ; CHECK IF HAS DATA 46 LOOPZ XMIT_3 ; WAIT TILL DONE 47 JNZ XMIT_4 48 DEC BL ; DECREMENT OUTER LOOP 49 JNZ SHORT XMIT_3 ; TRY AGAIN 50 INC BL ; SET ERROR FLAG 51 JMP SHORT XMIT_EXIT ; 8042 STUCK BUSY 52 53;----- GET THE DATA 54 55XMIT_4: SUB CX,CX ; ALLOW TIME FOR POSSIBLE 56 ; ERROR -> SYSTEM UNIT OR KEYBOARD 57XMIT_5: LOOP XMIT_5 58 IN AL,PORT_A 59 SUB CX,01H ; SET CX OTHER THAN ZERO 60XMIT_EXIT:
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61 RET 62XMIT_8042 ENDP
The function IN AL,PORT_A returns the proper 0xFA result and finally sets CX to 0xFFFF. So that part of the command went without problems(according to the documentation the command 0xFF gives 0xFA(command succeeded), then 0xAA(BAT succeeded) as a result)?
The very first " IN AL,PORT_A ; FLUSH DATA" during the XMIT_1 block flushes the 0xFA received, then the final read after XMIT_5 reads the incorrect 0xAA from the keyboard, instead of the correct 0xFA(which was discarded)???
Then it returns to the caller(KBD_RESET), which reads the 'result code', which is 0xAA. But it expects 0xFA and to read 0xAA at a later point in time?
1;--- KBD_RESET----------------------------------------------------------- 2; THIS PROCEDURE WILL SEND A SOFTWARE RESET TO THE KEYBOARD. : 3; SCAN CODE 0AAH SHOULD BE RETURNED TO THE PROCESSOR. : 4; SCAN CODE 065H IS DEFINED FOR MANUFACTURING TEST : 5;------------------------------------------------------------------------ 6 7KBD_RESET PROC NEAR 8 MOV AL,0FFH ; SET KEYBOARD RESET COMMAND 9 CALL XMIT_8042 ; GO ISSUE THE COMMAND 10 JCXZ G13 ; EXIT IF ERROR 11 12 CMP AL,KB_ACK 13 JNZ G13 14 15 MOV AL,0FDH ; ENABLE KEYBOARD INTERRUPTS 16 OUT INTA01,AL ; WRITE 8259 INTERRUPT MASK REGISTER 17 MOV @INTR_FLAG,0 ; RESET INTERRUPT INDICATOR 18 STI ; ENABLE INTERRUPTS 19 MOV BL,10 ; TRY FOR 400 MILLISECONDS 20 SUB CX,CX ; SETUP INTERRUPT TIMEOUT COUNT 21G11: 22 TEST @INTR_FLAG,02H ; DID A KEYBOARD INTERRUPT OCCUR 7 23 JNZ G12 ; YES - READ SCAN CODE RETURNED 24 LOOP GI1 ; NO - LOOP TILL TIMEOUT 25 26 DEC BL 27 JNZ G11 ; TRY AGAIN 28G12: 29 IN AL,PORT_A ; READ KEYBOARD SCAN CODE 30 MOV BL,AL ; SAVE SCAN CODE JUST READ 31G13: 32 RET ; RETURN TO CALLER 33 34KBD_RESET ENDP
That is supposed to happen at G12. But it never reaches that point, since the 0xAA is returned 'too soon'?
That would mean that the keyboard needs some kind of delay somewhere, or doubling the 0xFA result?
Edit: Even giving it the 0x00 byte in between(the data that's supposed to be discarded), it still errors out?
Edit: Whoops, forgot that my code skips the 0x00 byte outputted, because a flush of the buffer was executed after the 0xFA byte also, discarding the 0x00 byte just written.
Edit: Just implemented a little 100us delay between the 0xFA and 0xAA BAT completion output. That should fix the CX being zero(immediate interrupt when the command is sent)?
Edit: For some reason, CX is still zeroed when the KBD_RESET returns?
