superfury wrote:

I'm running the ET3000 BIOS on my UniPCemu emulator, but I notice some strange things being loaded into the ET3000 registers by the BIOS.

One thing I'm noticing is that, when starting any software in 640x480x256col mode(mode 2Eh in the ET3000 video mode list), it loads the Sequencer Memory Mode register with the value 6(Which specifies Planar memory mode). But in order for the memory mode to use Linear Graphics (according to the mode's documentation), it would need to be 0xE instead to supply the Linear Graphics mode(The rendering is set up correctly for 8-bit linear graphics).

Anyone knows why this strange value is loaded into that register? Is there a problem with my x86 emulation that causes this? Or does the BIOS actually need to load that value(it's a value loaded from the tables in it's ROM, which is directly after the other Graphics Controller registers in memory)? Is it missing some step somehow?

Sequencer register 4? My initial thought is that the BIOS knows what to do and there might be an expansion register somewhere else to select/override the mode to packed linear 8-bit mode. At least to me the 0x06 value makes sense because it has chain4 disabled so that two lower address bits do not force the plane, but of course this is not unchained either because in the linear mode you don't use the Map Mask register.

Well, my first thought was so too, but the only other register seeming that might do something is the segment select register at port 0x3CD, but it's set to 0x40, which means 64k mapping, not linear? I don't know of any other effective registers in this case? Registers 30h+ are ET4000 after all, and I can't find any other reference than this one in the documentation(WHATVGA documents and ET4000 datasheet). I can't find any ET3000 datasheet anywhere.

Edit: I see CRTC index 23 bit 7 and index 24 bit 3, which say something about some A8 line concerning 1MB memory, but otherwise nothing can be found.

3d4h index 23h (R/W): Extended start ET3000 bit 0 Cursor start address bit 16 1 Display start address bit 16 2 […]
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3d4h index 23h (R/W): Extended start ET3000
bit 0 Cursor start address bit 16
1 Display start address bit 16
2 Zoom start address bit 16
7 If set memory address 8 is output on the MBSL pin (allowing access to
1MB), if clear the blanking signal is output.

3d4h index 24h (R/W): Compatibility Control
bit 0 Enable Clock Translate if set
1 Clock Select bit 2. Bits 0-1 are in 3C2h/3CCh.
2 Enable tri-state for all output pins if set
3 Enable input A8 of 1MB DRAMs from the INTL output if set
4 Reserved
5 Enable external ROM CRTC translation if set
6 Enable Double Scan and Underline Attribute if set
7 Enable 6845 compatibility if set.

I think you are mixing two things here.

Linear vs banked - memory access:

banked: You can have the video memory mapped into a 64k window at A000:xxxx to access the whole video memory using 64k windows and select which bank to use

Linear: on a 286 and upwards, you can have the video memory mapped linearly for example 1MB block starting at 14MB. Super easy to access whole frame buffer in 386 pmode, it just looks like any other memory

Normal DOS games just use 64k segment and change the window (bank) to select which 64k window of the whole memory to select.

Planar vs Chained vs Linear - how the data is written from CPU to video memory

Planar : each memory write access to video memory address accesses same address in all four planes - thus only one fourth of the memory addresses are used because you have access to up to four planes planes at a time. So with only 64KB segment window, you can access 256KB of memory but in planes.

Chained : each memory write access to video memory address automatically selects one of the four planes to generate the mode13h 320x200 packed pixel mode, which automatically looks like to programmer that you have only 64KB of video memory but you can easily access the pixels linearly.

Linear: somehow the access to video memory for each 8-bit pixel could just be bank*64KB+offset, so it is linear, instead of planar or chained, for example pixeladdress=Y*640+X so bank=pixeladdress>>16; offset=pixeladdress&0xffff;

Well, if what you're saying is true, this complicates things:

1. Chain-4 vs linear: both essentially do the same: plane being addr%4 and offset being addr>>2 results in exactly the same as VRAM address being addressed by using linear memory address directly, this is 100% the same in UniPCemu: each dword read from memory to render is at an multiple of 4 in VRAM. Thus both methods render and access with 100% the same results in UniPCemu(I could add a seperate passthrough case for it, at the cost of more code, though).

2. If linear mode and banked are different, then the high 2 bits of the Segment Select Register at 0x3CD should have no business being able to select mode 2: Linear addressing, since it has nothing to do with the banking? Also, on the ET3000 no base address can be specified, according to the WHATVGA documentation(all I have and can find on the ET3000. I found the ET4000 one though, but since it's mostly different, it's useless as a reference on the ET3000). Can't find ANY datasheets on the ET3000:(