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First post, by superfury

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What effect does the D/B effect selecting 16-bit have (cleared) on a data segment, when addressed with an instruction with a 32-bit addressing size (like [EBP+00])? Is the address truncated to 16-bit? Or is it left alone (addressing 32-bit offset inside a (for stack and code read operations only) 16-bit offset)?

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UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io

Reply 1 of 2, by Ringding

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If I read chapter 17.1 in the original 386INTEL.TXT documentation correctly, the target segment's bit does not matter, it’s the one in CS that does. The data segment’s bit seems to matter only for expand-down and stack segments.

Reply 2 of 2, by superfury

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Ringding wrote on 2024-03-08, 14:34:

If I read chapter 17.1 in the original 386INTEL.TXT documentation correctly, the target segment's bit does not matter, it’s the one in CS that does. The data segment’s bit seems to matter only for expand-down and stack segments.

OK. So then it's actually correctly implemented now.

One thing that's changed since the last UniPCemu release was that stack switches to higher privilege (though a x86 call gate or interrupt) now checks the D/B bit to load either SP or ESP based on that (previously it was using the TSS size being 32-bit or 16-bit, which is incorrect behaviour). Of course, loading ESP from a 16-bit TSS (D/B set in SS descriptor) clears the top bits and loading SP from a 32-bit TSS (D/B cleared in SS descriptor) now get the truncated value (SP ignoring the top bits in the TSS and ESP clearing the top bits of the TSS in such cases).

Author of the UniPCemu emulator.
UniPCemu Git repository
UniPCemu for Android, Windows, PSP, Vita and Switch on itch.io