Are the values of the CPU's CPL and SS.DPL exactly as in the memory map loaded during RSM? Or is SS.DPL set to CPL?

Afaik Pentium just loads SS.DPL into CPL, while Pentium Pro loads it from the CPL field instead (ignoring SS.DPL until used for loading directly using documented methods like jumps, calls etc.)?

What about the other undocumented fields in the RSM save state map on P6?
https://www.sandpile.org/x86/smm.htm

- A20M#
- SMM_status
- sreg_status0
- sreg_status1

Also, what about invalid combinations in CR0? Are they applied without questions or faulting (e.g. Paging without PE-bit)?