Wow, even 50MHz is pushing the system to it's limits. I guess almost nothing will be compatible with this bus speed. VLB was just not built for this kind of operation. Physics won't allow it.

Paar wrote on 2024-02-25, 19:39:

Wow, even 50MHz is pushing the system to it's limits. I guess almost nothing will be compatible with this bus speed. VLB was just not built for this kind of operation. Physics won't allow it.

50MHz works for me in that board with 2 cards. But cache does not run anymore in 2-1-2, so in the end 4x40 always wins against 3x50 with the Am5x86, because not only the internal clock is faster, but also at 40MHz lowest (best) timings work.
But I could try 3x50 for Am5x86 again, and then compare it to 2x50 on an IBM 5x86. (Remark I thought the IBM is stable at 3x40, but it is not, Windows 98 crashes after one or two minutes.)

Well I meant nothing will work with 60MHz and higher, of course 50MHz will work with if the timings are loose enough. Howver I'm not an overclocker, I run everything stock and am happy with it 😀.

Paar wrote on 2024-02-25, 19:59:

Well I meant nothing will work with 60MHz and higher, of course 50MHz will work with if the timings are loose enough. Howver I'm not an overclocker, I run everything stock and am happy with it 😀.

I am not sure about that "nothing will work with 60MHz and higher". Maybe with only one vesa local bus card it will work. I will try it.

You could try running some tests from CD or floppies. I wonder how stable a VLB graphics card will be.

Paar wrote on 2024-02-25, 20:06:

You could try running some tests from CD or floppies. I wonder how stable a VLB graphics card will be.

Yes, but I miss a ISA IDE card at the moment.
So I can only try with an ISA graphics card 😁

Well, ISA IDE controller should be OK if you select proper divider for the ISA bus or force it at 8 MHz. Most of the VLB boards should have this option.

I recently found a scan of a magazine from 1992 in which they claim the VLB is designed to operate at speeds up to 66MHz. Well, maybe that was the original intention of the designers... I very much doubt it can be done unless the voltage is reduced (i.e. 3.3 - 3.6 V which was already being considered for the next generation of processors) and other design constraints are implemented. A few ones that I can think of -and that would have facilitated higher operating frequencies- are having only one VLB slot, placement of the processor very close to the slot itself, an extra grounded backplane, etc... Of course, since the 486 bus was already reaching its limits at 50MHz and the Pentium switched to a 64 bit bus, investing more resources into VLB was kind of useless. Had the Pentium debuted with a 66MHz, 32 bit and 3.3v bus, then -maybe- a VLB 3.0 would have made much more sense.

One thing I find odd is that no chipset manufacturer in the VLB era ever considered implementing the IDE controller inside the chipset for higher performance. That would have made the VLB solely a dedicated graphic port, as it happened with AGP a few years later.

MSxyz wrote on 2024-04-09, 08:53:

I recently found a scan of a magazine from 1992 in which they claim the VLB is designed to operate at speeds up to 66MHz. Well, maybe that was the original intention of the designers... I very much doubt it can be done unless the voltage is reduced (i.e. 3.3 - 3.6 V which was already being considered for the next generation of processors) and other design constraints are implemented. A few ones that I can think of -and that would have facilitated higher operating frequencies- are having only one VLB slot, placement of the processor very close to the slot itself, an extra grounded backplane, etc... Of course, since the 486 bus was already reaching its limits at 50MHz and the Pentium switched to a 64 bit bus, investing more resources into VLB was kind of useless. Had the Pentium debuted with a 66MHz, 32 bit and 3.3v bus, then -maybe- a VLB 3.0 would have made much more sense.

One thing I find odd is that no chipset manufacturer in the VLB era ever considered implementing the IDE controller inside the chipset for higher performance. That would have made the VLB solely a dedicated graphic port, as it happened with AGP a few years later.

Somebody here on Vogons claimed to run a VLB graphics card at 80MHz. I don't have a link at hand, too lazy to search.
Also user pshipkov run VLB boards at 60 and 66MHz bus, but not the Asus VL/I-486SV2GX4, so that board does not seem to allow it.
After writing that thread I remembered (also wrote it here on Vogons 🤣!), that the board started to smell at 60MHz.
So I will not try it again, I really like my SV2GX4.

Paar wrote on 2024-02-25, 19:39:

Physics won't allow it.

Physics will do as it's told.

I have run i/o and vga on 60Mhz VLB on a BEK V439, it took a hell of a lot of cherry picking though. Pretty much anything that needs a waitstate set below 50mhz isn't capable. Unfortunately I took that machine apart some years ago and am no longer clear what cards it was, beyond remembering one was GD5429 and one was a UMC chip i/o

Edit: so I remembered I had a pic on my phone of two cards I found stored together, when normally I had io and vga in separate storage, the only reason I can think of I might have done that is because they were the pair that worked at 60... well that's the side I'd put my money down on, but also possible they were just together in a random system that I pulled apart after vga and io box were full at the time or something. Also note that even if these are the cards I got 60mhz out of, they might not get 60 on another board, minor differences, and also different specimens of these two cards may not be so lucky in the silicon lottery, so may not do it. So basically, do your own cherrypicking, 'coz guarantees are not to be had.

MSxyz wrote on 2024-04-09, 08:53:

One thing I find odd is that no chipset manufacturer in the VLB era ever considered implementing the IDE controller inside the chipset for higher performance. That would have made the VLB solely a dedicated graphic port, as it happened with AGP a few years later.

Some late 486 chipsets have an integrated IDE port that is somehow connected to the frontside bus, and not configured using PCI configuration space. They call it "local bus IDE controller". This applies to the SiS 496/7 and the UMC8881/UMC8886. Although the UMC8886 is kind of borderline, as in the latest silicon revision, the IDE interface is configured using PCI configuration space instead of legacy I/O ports.

mkarcher wrote on 2024-04-09, 18:26:

MSxyz wrote on 2024-04-09, 08:53:

One thing I find odd is that no chipset manufacturer in the VLB era ever considered implementing the IDE controller inside the chipset for higher performance. That would have made the VLB solely a dedicated graphic port, as it happened with AGP a few years later.

Some late 486 chipsets have an integrated IDE port that is somehow connected to the frontside bus, and not configured using PCI configuration space. They call it "local bus IDE controller". This applies to the SiS 496/7 and the UMC8881/UMC8886. Although the UMC8886 is kind of borderline, as in the latest silicon revision, the IDE interface is configured using PCI configuration space instead of legacy I/O ports.

Every day there's something new to learn 😀

BitWrangler wrote on 2024-04-09, 18:18:

Paar wrote on 2024-02-25, 19:39:

Physics won't allow it.

Physics will do as it's told.

Actually it's the other way around. There's theory and then there's reality. Take the good old TTL for example... In theory 0 volt = logical zero, 5 volt = logical one. In practice, anything below 1 volt = logical zero, anything above 4 volt (or 4.5) = logical one. At the same time, ramping up or ramping down a signal is not immediate; it takes time... If you don't give the bus enough time, you will measure a voltage that is neither zero nor one. And this not even taking into account interferences, noise, reactance... That's why electrical buses evolved to use lower voltages, least you have to relax the timings using wait states.

On a side note, when the first telegraph message was sent through 3200Km of undersea cable across the Atlantic in 1858, it took two minutes to send just one Morse coded word! That's a lot of wait states!!! 😀

VL/I-486SVGO(X4)/SV2GX4 support these jumpers to help with higher frequencies....
Wait State 0/1
<=33MHz or >33MHz
No Clock Delay/Delay

One of the best boards to try > 33MHz on.

The ark1000vl is reasonably stable at 60mhz. Maybe some et4000w32ps have a chance.

I’d have to double check, but I think vlb 2.0 worked at 66mhz if there was only one device and it was integrated onto the board. Vlb 2.0 was never really adopted by anything though. I think a few boards and cards claim to support it, but don’t implement the full specs

MSxyz wrote on 2024-04-10, 08:52:

Actually it's the other way around. There's theory and then there's reality. Take the good old TTL for example... In theory 0 volt = logical zero, 5 volt = logical one. In practice, anything below 1 volt = logical zero, anything above 4 volt (or 4.5) = logical one.

Get your facts right if you are going to lecture me, nominal spec is under 0.8V for low, over 2.0V for high, but in practice held to 0.4V low 2.4V high for 0.4V noise tolerance.

You re right. I mixed up the high value with pseudo ECL. That's what happens when I use my memory instead of doublechecking what I seem to remember.
Also, apologies if it seemed I was lecturing... I was only commenting that "Physics will do as it's told" seems a bit strong statement. Usually its engineers that have to find a way around, sometimes in a creative way. Peace.