red-ray wrote on 2020-10-15, 14:15:

The last time I recall checking was on 22-Feb-2006 on a Gigabyte 7DPXDW-P system with an AMD Athlon @ 2.00 GHz + a Duron @ 1.60 GHz.

luckybob wrote on 2020-10-15, 17:48:

NO. No, they don't. If you have mismatched CPU's it will run at the slower speed. Period. End of discussion. It's a fracking miracle it even posts with mismatched processors like that. NT/2K will complain about mismatched processors and might not be stable. XP will NOT boot unless the processors are PERFECTLY matching.

Given my earlier post I can't see how this can be correct. Using the save file and running in SIV test mode I get as below which clearly shows the two CPUs are different and running at different speeds.

Heck, with multi-core CPUs the cores can run at different speeds so Windows MUST implicitly support different sockets at different speeds.

After pondering Intel CPUs running at different speeds I am concerned about the QPC. It's possible the TSC get's used for the QPC and suspect the two sockets having different TSCs may cause issues, then again keeping the two TSCs I phase may also be an issue. I also recall XP and 2003 using different QPCs for the same system.

red-ray wrote on 2020-10-16, 07:23:

After pondering CPUs running at different speeds I am concerned about the QPC. It's possible the TSC get's used for the QPC and suspect the two sockets having different TSCs may cause issues, then again keeping the two TSCs I phase may also be an issue. I also recall XP and 2003 using different QPCs for the same system.

I recall this being a problem when multicore CPUs came around, and maybe again later when the 'turbo boost' schemes came out. OS updates were issued to fix it. For instance, I had Win2000 SP4 installed on an Athlon 64 X2 and used a 3rd party utility to do throttling. Before installing the updates, some games/animations would play at the wrong speed. AMD changed the behavior on Phenoms so that TSC could be locked to a certain frequency regardless of what speed the CPU was running (the BIOS would normally set this option).

There was also something about a game that started crashing because the developers had used RDTSC directly, instead of using the OS function, and it was returning different results on different cores. Maybe that one was an Intel CPU.

red-ray wrote on 2020-10-15, 21:18:

Hanamichi wrote on 2020-10-15, 16:30:

red-ray wrote on 2020-10-15, 14:15:

From your post I assume you have a system with different speed CPUs and I am wondering if my SIV utility correctly deals with this, please will you try it and post the two Menu->File->Save Local files so I can check?

Sure I can do this at weekend, does the OS matter between XP/2000/NT?

Thank you, the OS does not really matter, but if the system is multi-boot my ordered preference is 2003 -> XP -> 2000 -> NT4. I prefer the newer OSes as they tend to have more recent CPU µCode.

The Menu->Machine->CPU Benchmark panel will tell you how the CPU speeds compare.

No problem, I'll try XP tomorrow and see how it goes.

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red-ray wrote on 2020-10-16, 21:41:

No, by the time there were multi-core CPUs that could change speed they all had an invariant TSC (TSCIV) so the TSC speed does not change as the CPU speed changes. Further the systems with these have/use the ACPI or HPET timers for the QPC clock.

This is not true. AMD K8 had no invariant TSC but used powernow/cool&quiet to dynamically change CPU core clock. That's why you had to use AMD dual-core optimizer or /USEPMTIMER switch in boot.ini to overcome TSC related problems.

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red-ray wrote on 2020-10-17, 07:03:

AFAIK it's only mobile CPUs that have powernow/cool&quiet and these can't be used in the multi-socket systems this thread is about,...

No, The desktop/server Athlon 64 processors also used Cool&Quiet. More precisely Cool&Quiet is the name of the power saving technology used in the desktop and server segments.
https://en.wikipedia.org/wiki/Cool%27n%27Quiet

Due to their different usage, Cool'n'Quiet refers to desktop and server chips, while PowerNow! is used for mobile chips; the technologies are similar but not identical. This technology was also introduced on "e-stepping" Opterons, however it is called Optimized Power Management, which is essentially a re-tooled Cool'n'Quiet scheme designed to work with registered memory.

red-ray wrote on 2020-10-17, 07:03:

further by default such systems use the 3.580 MHz ACPI timer as the QPC clock rather than the TSC.

It depends on OS, and Windows 2000/XP might use TSC for QPC even when it was not working properly unless it was explicitly defined otherwise:
https://docs.microsoft.com/en-us/windows/win3 … indows-versions

QPC is available on Windows XP and Windows 2000 and works well on most systems. However, some hardware systems' BIOS didn't indicate the hardware CPU characteristics correctly (a non-invariant TSC), and some multi-core or multi-processor systems used processors with TSCs that couldn't be synchronized across cores. Systems with flawed firmware that run these versions of Windows might not provide the same QPC reading on different cores if they used the TSC as the basis for QPC.

https://docs.microsoft.com/en-us/troubleshoot … -perform-poorly

This article provides a resolution for the problem occurs on 32-bit computers and x64-based computers that have the AMD Cool'n'Quiet technology enabled in the BIOS...

This problem occurs when the computer has the AMD Cool'n'Quiet technology (AMD dual cores) enabled in the BIOS or some Intel multi-core processors. Multi-core or multiprocessor systems may encounter Time Stamp Counter (TSC) drift when the time between different cores is not synchronized. The operating systems that use TSC as a timekeeping resource may experience the issue...

To work around this problem, update the BIOS on the computer. Or, modify the Boot.ini file to use the /usepmtimer switch. To do this, follow these steps:

By the time there were multi-core CPUs that could change speed it became clear that an invariant TSC (TSCIV) was needed so the TSC speed does not change as the CPU speed changes.

There were probably a few multi-core CPUs that did not have TSCIV, but this is not relevant to running SMP P2/P3 systems with different sockets running at different speeds.

In general if there is more than one CPU it's sensible to use the ACPI or HPET timers for the QPC clock.

DRUM ROLL please..... well everything went as expected, no explosions.

That is when I worked out that the motherboard can't boot from an OEM Windows XP install disc but can from an official 2000 install disc. That wasted some time arghh
So I actually installed Win 2000 from scratch with the CPUs mismatched. No issues, no warnings, no crashes.

Anyway attached information requested, so far so good.

Note: I put a single 512MB ECC memory stick in and ran loose memory timings at stock 100 FSB so SuperPI can be quite a bit better then this. To ensure no instability interfering with the results.
@red-ray your program seemed to handle the mismatch fine. Had to use W2K due to the above issue at the moment.

Moving forward I'll run Q3A SMP ON/OFF, overclock a bit and set the multiplier to 3.5 on the 700MHZ CPU to show a bigger difference.

SIVX summary:

SuperPI with affinity set for each corresponding CPU.

SIVX and CPUZ reports:
(CPUZ seems get a bit confused with one or two CPUs installed)

2:10 on a 700 and 3:00 on a 900 is almost a perfect ratio between 9 & 700mhz.

i have to admit, this is fucking with my head.

I wonder if P4 xeons will work like this? I have a PC-DL i need to test before I box it up for storage...

Hanamichi wrote on 2020-10-17, 19:59:

@red-ray your program seemed to handle the mismatch fine. Had to use W2K due to the above issue at the moment.

Thank you and W2K is fine. As you said SIV got the speeds correct and [CPU Benchmark] showed CPU-1 is appropriately faster than CPU-0.

SIV came up with To be To be Filled as the motherboard name 🙁, please post C:\Documents and Settings\SMPKING\Desktop\SIVX\SIV_S2DG2.dmi so I can try and improve this.

luckybob wrote on 2020-10-17, 21:20:

I wonder if P4 xeons will work like this? I have a PC-DL i need to test before I box it up for storage...

I suspect no. My Compaq Workstation W8000 won't post with a Intel Xeon MP (Gallatin) 2.70GHz SL79Z + Xeon MP (Gallatin) 3.00 GHz SL79V, but your mileage may vary.

At the moment it's got 2 x SL79Z while I am looking for another cheap SL79V

I can get the dmi file next run no problem, CPUZ had the same issue so it may just be the obscure motherboard.

Regarding the P4s that's Interesting, complete guess but the whole mix and match restrictions could come from lack of validation and possible unforseen issues.

So a major server and business hardware provider with support contracts will lock their motherboards down pretty tight. Like HP, Compaq, Dell, Cisco etc

On the other hand a consumer/workstation/small server oriented manufacturer will probably want to offer compatibility for future upgrades without needing updates/unlocks. So you may have more of a chance with ASUS, Supermicro, Iwill, Abit and Tyan etc.

Hanamichi wrote on 2020-10-17, 23:10:

I can get the dmi file next run no problem, CPUZ had the same issue so it may just be the obscure motherboard.

OK, I have just uploaded SIV 5.53 Beta-00 which should do better as once I looked at the save file I was able to improve the SIO reporting so please use this to generate new save files.

The issue with there being no S2DG2 is that the SMBIOS data is poor/bad. Is there a later BIOS available?

It would be interesting to see what other Supermicro S2DG boards report, so if anyone has one please post the two SIV save files.

Round 2.

900MHz Xeon 2MB @ x9 Multi (locked)
700MHz Xeon 1MB @ x3 Multi set on the motherboard (lowest possible)

Stable, no stability issues and you can really tell when application sets the affinity to the slower CPU.

@red-ray the beta has fixed the CPU2 temperature
All hardware reading apps get confused when the multi is set low when reporting the FSB and RAM speeds.
As far as I know it is the last bios.

112MHz FSB set in the bios:
(SIV32X Beta)

66MHz FSB set by CPUCool:
(SIV32X Old)

@red-ray here are the outputs using the SIV32X beta:

(I had to rename to dmi.txt to upload)

Every time the system is booted the second slot CPU gets elected as the BSP processor sadly.

Silly question:

I have a handy "IOSS RD1 Bios Savior" as below, it's a DIP Flash ROM with a switch allowing dual bios chips with a selector switch.
My one is a 2Mbit model, if the motherboard has a 1Mbit Flash ROM (labels are obscuring the motherboard chip) can I still use this and override warnings when flashing to the 2Mbit chip?

Hanamichi wrote on 2020-10-18, 14:43:

All hardware reading apps get confused when the multi is set low when reporting the FSB and RAM speeds. (I had to rename to dmi.txt to upload)

Thank you and the x11 rather than x3 was a bugette in SIV. With >= stepping 3 the rules change, my code was correct for Coppermine (Model 0x08), but not Cascades (Model 0x0A) and SIV was using wonky >= stepping 3 code 🙁

In the attached SIV32X 5.53 BIOS-01 test SIV I should have fixed it, have I? I should also have also updated things to report the BIOS version as R1.6.

I find the best option is to ZIP all the files and attach the .ZIP file.

Hanamichi wrote on 2020-10-18, 14:53:

if the motherboard has a 1Mbit Flash ROM (labels are obscuring the motherboard chip)

Looking at [Machine] the BIOS size is 256KB, so I expect it's a 2Mb chip on the motherboard.

In a functional SMP OS, dual CPUs explicitly *cannot* run the same process or thread at the same time, so there's no fundamental reason that they should have to be at the same clock. It makes sense that it could introduce software timing bugs though, like with that WinAPI timer function that was mentioned above.

I imagine that multithreaded programs could see bugs in this situation, but that comes down to their own programming. Multithreaded programs assume responsibility for not letting their threads crash each other. Some are more stable than others.

In principle, I think two independent processes shouldn't have any problem since they're operating in separate memory space and register state.
But it's not officially supported, nobody tests it, there might be miscellaneous caveats like the timing issue, and any serious company will scream at you for doing it because they don't like fun.

I ran two asymmetrically clocked PIIs for a short time in WinXP on my Tyan Tiger 100 - one at 350 the other at 450. I did not observe any problems, but this configuration was only a temporary affair.

Round 3:

Used your 5.53 version red-ray. Seems to have fixed the issues.
Do you have a spreadsheet of CPU benchmark results or know the ballpark figures for a 386DX and 486 33/40?
Hoping that one of my results below is comparable.

@ 112Mhz FSB

@ 112Mhz FSB, Internal Cache disabled.

@ 66Mhz FSB, Internal Cache disabled.