Reply 100 of 113, by LightStruk
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ragefury32 wrote on 2021-01-07, 04:46:Wait, did I read their block diagrams incorrectly? I went through their Youtube channel and they had an almost 2 hour deep dive of the EX2. It's in Mandarin Chinese, but the slides are in English.
https://www.youtube.com/watch?v=AB9paYWC5QoThe way how I interpret the architecture is that the crossbar I/O setup can be mapped to either cores at any time, and the master core has access to re-map if needed, so they share the entire I/O fabric - the idea is that it was supposed to run 2 segregated OS in the same hardware, but with the more powerful one moderating I/O access to the weaker one. You "should" be able to put a PCIe video card (like the Vortex86 VGA card) onto the EX2, map it to the slave, map the GPIO pins for the ISA sound chip to it as well and then use USB (which is mapped to the master) for Wifi and/or Bluetooth for the controller, then maybe have the master moderate keystokes/controller positions/whatever to the slave. Then the master can write to that LCD framebuffer for implementing menus. The awkward thing about the Vortex86EX2 deep dive is that they never really talked about what CPU instructions are supported in the core.
I've also seen that video, and I agree with everything you wrote here, except for the bit about mapping ISA to the slave core. The block diagram on the product page clearly only shows ISA on the Master core, and the fact sheet for the Slave core doesn't list ISA as an option either, while the fact sheet for the Master core definitely does list ISA.
ragefury32 wrote on 2021-01-07, 04:46:Okay, so I am going to make 2 assumptions: a) The slave core in the EX2 is basically the same core as the one on the EX (which i […]
Okay, so I am going to make 2 assumptions:
a) The slave core in the EX2 is basically the same core as the one on the EX (which is used in the 86duino) - hmmm, /proc/cpuinfo for it exists here, and we can see if it's a i586 or an i686 if we look at the eflags:http://www.86duino.com/?page_id=85/installati … g-1/linux-image
The ones to note:
fpu tsc cx8 sep cmov mmx
FPU/TSC is pretty standard fare for anything p5 and above.
Note that it has cx8 (common on p5), mmx (that's on the p55c and later), cmov (that's a P6 class instruction) but mtrr is not there. So it's probably i686 kosher, but you can't mess with the MTRR to combine block transfers like you can on a K6-2 or a Pentium 2+, although you'll probably need to play around with one to determine that.b) The master core is an EX core but with more stuff inside, and here's the /proc/cpuinfo with eflags.
https://tortoiseit.blogspot.com/2020/09/infor … 86-ex2-soc.html
The ones to note:
fpu pse tsc msr pae cx8 apic sep pge cmov pat mmx fxsr sse sse2 nx cpuid pni ssse3
FPU/tsc is assumed, PSE is a p5/p6 option, it does have the SSE-SSSE3 stuff, PAE/NX (usually found together in anything newer than a Banias Pentium-M).
So basically, it claims about the same features as a Yonah Pentium-M (well, Core Solo but with much less L2)So no, the EX2 is probably more powerful than you think....but D&MP's technical information is rather vague and doesn't answer the tough questions.
Thank you for finding the /proc/cpuinfo for the master core. With SSE2 and SSE3, it would be fun to benchmark it against a P3-600, just to see how it compares clock-for-clock.