I am working through a similar situation. I have a MICROMATION TECHNOLOGY, INC. 80386-WBH (http://www.win3x.org/uh19/motherboard/show/3688) motherboard with the OPTi 82C391/392 WB chip set. It came with 64Kb WB motherboard cache. Benchmarked it when I found it and the 64Kb cache was working.
I upgraded it to MR BIOS and it posted & booted. I was upgrading a couple boards that day and didn't really investigate too deeply because I had other boards that were being more fussy about MR BIOS.
Later I tried to upgrade the cache to 256MB and it didn't detect. I tried putting the 64Kb cache back in place and it wasn't stable. It would post with the most relaxed timings but was not stable. I thought I may have ordered the wrong sram & ruined the 64kb chips with a dry January ESD, but I had been careful. There was definitely a drop off in performance without the motherboard cache, which made me unhappy.
When a good price showed up on SRAM in February, I bought a second set of SRAM chips for a 256Kb cache, but it was from China and took a 10 weeks to arrive.
In the meantime, I sold a pair of spare AM5x86 P75 chips and used the proceeds to get a 486DLC chips from Czech. It works, but it's hot and I was not able to get the L1 or L2 to work with it
The second set of SRAM arrived, but I cannot get it to detect either, so I don't think it is related to the chips.
When looking at the pins after changing the jumpers, I noticed that pin 3 for both JP7 and JP10 looked low. Checking the back, looked like there was damage.
Seems like the middle pins on the jumpers connect to the IC labeled P9236 / DM74LS244N or the tag ram
Seems like the 1 & 3 pins on the jumpers connect to the OPTi F82C206L chip through RP10
Except for the ones that look damaged
JP7 -Pin3 (disconnected )
JP10-Pin3 (ground)
I started to clean out the post hole for JP10 Pin3, but I'm worried that I'm making things worse and I don't need JP10-Pin3 unless I am doing a 32K cache, so as long as it's not causing a damaging short, maybe I can leave it as is.
I need JP7 -Pin3 to be connected. The trace from JP7 -Pin3 goes to a via and JP3 pin3 is not connected to the via, so there a break in there. The via connects to the CPU (Pin L13 if I'm counting things correctly)
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