This is exciting. I've been itching to get my BL3 onto a PGA-132 interposer. I have an interposer with a slightly larger surface area which should just fit an adjustable VRM that I have on hand now. Sadly, our foundation waterproofing and drainage project drags on. Trying to do all the work myself and manage 3 kids is interesting. At times, they have actively sabotaged the trenches.

For your case, are you able to solder on a BL3-75 that you know works at 100 MHz on another system? Will the BL3 from the DTK work at 100 MHz in the Cougar with your desired quantity of RAM, for example?

I also have found a large variance in overclockability of the IBM BL3-75 chips.

feipoa wrote on 2022-08-30, 22:16:

Sadly, our foundation waterproofing and drainage project drags on. Trying to do all the work myself and manage 3 kids is interesting. At times, they have actively sabotaged the trenches.

Maan 😖
What is the percentage of completion of that project ?
I will be interested to see how your Acer Panda handles BL3.

feipoa wrote on 2022-08-30, 22:16:

For your case, are you able to solder on a BL3-75 that you know works at 100 MHz on another system? Will the BL3 from the DTK work at 100 MHz in the Cougar with your desired quantity of RAM, for example?

If the Cougar board had proper 386 socket everything would be much easer with testing different CPUs, but the need to solder stuff around greatly limits my options. Even the best quality PCBs can start loosing solder pads after few rounds of action only.
The CPU i soldered was able to handle 100MHz with active cooling on other mobos so it should be fine on the Cougar too.
Will know for sure in the next few days.

feipoa wrote on 2022-08-30, 22:16:

I also have found a large variance in overclockability of the IBM BL3-75 chips.

Yes.
This makes things unpleasant - one cannot assume that spending $ on a BL3 will bring the desired ROI.

@chadti99
I am thinking to run the remaining M919+1Mb_L2_cache+POD100 benchmarks tonight.
Doing a preflight check in case you are doing something like that already.

pshipkov wrote on 2022-08-31, 00:39:

@chadti99
I am thinking to run the remaining M919+1Mb_L2_cache+POD100 benchmarks tonight.
Doing a preflight check in case you are doing something like that already.

All you man, go for it!

I swapped the CPU back to AMD and I’ve been able to complete timedemos in GLQuake with the Voodoo4.

Did.
The 1Mb L2 cache helps for DOS interactive graphics and Windows GUI.
For some reason complex compute tests started failing until DRAM READ/WRITE STATE was set to 1. This of course made things slower than 256Kb L2 cache with 0 wait states for DRAM.

chadti99: So the flakely support of the POD is what was goofing up the Voodoo4 + m919? Does the Voodoo4 work in other UMC 8881 based systems, or just the M919? If the Voodoo4 works, how about the Voodoo5?

pshipkov: estimated completion time for the foundation - perhaps mid September if all goes according to plan, but I'll still have a massive mound of dirt to get rid of. I'm going to try to talk the neighbours into taking it. I noticed their back yard is sloping and the clay-based soil I have to offer will help remedy this. It is probably around 5 yards.

In the past when you tested m919 w/1M and DRAM at 0WS, did you run the same tests as your most recent run? Are you using the same memory module? I assume you're doing 3x60 on the AMD?

Early on Chadti said m919 liked the V4 only and that is with Am5x86.

Best of luck with the house work.

The issue with M919 complex compute tests failing with DRAM R/W STATE = 0 is related to 1mb L2 cache and POD CPU.
If switch back to Am5x86 - everything passes with 0 wait states for DRAM.

Sorry if getting too far away from topic, but IIRC, the PODs will revert to 1x multiplier if tacho signal from fan is missing. How would a 66Mhz POD perform in 66MHz FSB if possible?

Attached are some images I took in preparation of the BL3 386 interposer hack. Another user commented that the Jaton has only 4 Vcc pins connected, but I won't be sure of the no-name interposer until I desolder the 386DX. Since there are four empty filter capacitor pads on the bottom of the PCB, I kind of assume there's also only 4 Vcc pins going to the QFP.

I've layed out the two interposers next to each other with the VRM on the PCB. The Jaton has the QFP leg over one of the VRM pins, but it might still be possible to use in this fashion. The Jaton does have more vias on the top which could increase the probability of a short. The VRM shown is the AM1117 adjustable.

I've shown a trimmer from my bin, but most likely I'd source a trimmer with a side screw for easier voltage adjustment.

For the Evergreen Am5x86-133 interposer, I noticed that they always use a 100 uF tantalum for Vin and either 8x10 uF tantalum for Vout or 4x10 uF tantalum for Vout (different PCB revision). So perhaps I should copy this approach? If so, then add a 10 uF cap to each detached QFP Vcc lead? The Evergreen interposer also uses the 1117 VRM, but a different brand, EZ1117. Should I add a bypass capacitor to the adjust pin for ripple reduction, and if so, what value? 10 uF? Vout/Vref ~3.

pshipkov wrote on 2022-08-31, 13:50:

The issue with M919 complex compute tests failing with DRAM R/W STATE = 0 is related to 1mb L2 cache and POD CPU.
If switch back to Am5x86 - everything passes with 0 wait states for DRAM.

Hi Pshipkov, just double checking, I need 1ws for DRAM read for stable operation at 180MHz(60x3) is this the same for you?

@feipoa, I might of found, still needs testing, stable Voodoo4 operation with the bios that pshipkov posted and with an AMD 5x86 at 180MHz on the m919. I’m not sure I’ve tried the Voodoo4 on any other UMC boards other than the Biostar UUD. I’ll have to go back and check now. I did get it running on the LSD but that is a SiS board as you know.

H3nrik V! wrote on 2022-08-31, 21:21:

Sorry if getting too far away from topic, but IIRC, the PODs will revert to 1x multiplier if tacho signal from fan is missing. How would a 66Mhz POD perform in 66MHz FSB if possible?

I think I’ve tried it and it’s generally slower than 83MHz but I’d need to re-check.

Chadti99 wrote on 2022-09-01, 02:00:

H3nrik V! wrote on 2022-08-31, 21:21:

Sorry if getting too far away from topic, but IIRC, the PODs will revert to 1x multiplier if tacho signal from fan is missing. How would a 66Mhz POD perform in 66MHz FSB if possible?

I think I’ve tried it and it’s generally slower than 83MHz but I’d need to re-check.

Yeah, it could go both ways, just figured that the 17 extra MHz would be no match to the 100% increase in FSB ... All thoug the POD may be so severely bandwith-limited even at 66 MHz FSB on a 486 board. 🤣

@H3nrik V!
I tried that before.
All apps on this class hardware, except some HW accelerated Win GUI features, are hard CPU bound. So higher FSB frequency << higher CPU clock speed.

@Chadti99
I can run DOS interactive graphic and Windows GUI tests at 0 DRAM waits. The harder tests however are not go until DRAM R/W WAITS = 1.

@Feipoa
Thanks for the photos and info. It will be really interesting if this stuff makes a difference.

My understanding is that there are only 4 VCC pings connected. I remember slapping on the the under side 10 mF capacitors - there was no observable difference.
It makes sense to use that Evergreen adapter as a guide since there is nothing else out there to follow.
No idea about your last question.

pshipkov wrote on 2022-09-01, 06:36:

@Chadti99
I can run DOS interactive graphic and Windows GUI tests at 0 DRAM waits. The harder tests however are not go until DRAM R/W WAITS = 1.

I’ve only been able to pull off a quake timedemo once at 0 DRAM waits on both read and write. Most of my modules won’t even let me boot if I don’t have DRAM read at 1ws. Can you share what specific memory you’re having success with?

pshipkov wrote on 2022-09-01, 06:36:

@H3nrik V!
I tried that before.
All apps on this class hardware, except some HW accelerated Win GUI features, are hard CPU bound. So higher FSB frequency << higher CPU clock speed.

Oh, that clarifies, thanks.

Chadti99 wrote on 2022-09-01, 07:23:

I’ve only been able to pull off a quake timedemo once at 0 DRAM waits on both read and write. Most of my modules won’t even let me boot if I don’t have DRAM read at 1ws. Can you share what specific memory you’re having success with?

For 1mb l2 cache at 3x60:
With am5x86 cpu all tests pass with dram r/w states = 0.
With pod100 - as mentioned above.

Most ram modules do it. I use the type i sent you (lgs brand) and this one:

Thanks, that LG stick you sent me got me into windows at the fastest timings! GLQuake crashed though 🤣.

One thing I’ve noticed. In some cases DOS 7 pulls 0.1 better frames than DOS 6.2 on some boards.

I’m able to hit 21.5 on fastest dram timings in DOs 7 on this board.

Cool. Too bad it is not fully stable.
So, are there annoying issues with the latest changes - BIOS, etc, or things are as advertised ?

pshipkov wrote on 2022-09-01, 19:16:

Cool. Too bad it is not fully stable.
So, are there annoying issues with the latest changes - BIOS, etc, or things are as advertised ?

1.png

Yah would be nice if it was stable at those timings.
But yes, in general quite a few of my issues were resolved with the bios you provided.

Was hoping to see an improvement in GLQuake scores at 180 but it seems in line with the other 180 capable boards. Maybe it did pick up one frame which is about where I would expect it I guess. 30 vs 31fps with same settings.

Did you try the bios from 1998 and found it no good for over clocking? This question applies to pshipkiv and chadti99.