Well the PALs are old tech by now, everything has moved to GALs back in the '90 or so. So I guess the only way to read it would be to use one of those scanning methods. This has pros and cons:
Pros: It will work even on secured device, 16L8 has no registers so it can only do simple logic terms. The only issue is output enable on the pins but it's rarely used and maybe the scanners deal with it too.
Cons: The scan will be partially invalid because we know the pin 13 output seems to be stuck. But we also know it should be a simple non-inverting pass-through frompin 11 to 13, so that can be just added to the result manually.

That being said it's a whole new project probably. So consider adding a simple gate for that pin with extra logic chip and maybe that will be easier in the end.

Deunan wrote on Yesterday, 20:42:

But we also know it should be a simple non-inverting pass-through frompin 11 to 13, so that can be just added to the result manually.

That's not completely correct. The PAL should implement a gated pass-through. The PAL needs to receive the "/INTERNAL" signal from the EGA card, which is an active-low signal that enables the EGA-internal driver for the monitor output. If that pin is high, the EGA releases the monitor output (all of it, all 6 color bits and the 2 sync bits) and passes control to the device at the feature connector. On the original IBM design, this is implemented using a 74LS244 with both enable pins tied together to /INTERNAL. So the missing equation would need to also contain the appropriate output enable qualification.

It seems this EGA card uses that PAL in a way that different outputs have different enable conditions, so pin 11 was not used as global output enable. At the moment, I have no inclination to do further reverse engineering of the traces on that card to guess PAL equations, but if you were to try to reconstruct the PAL from a combinatorial dump, you would need to find /INTERNAL (which is at pin 27 on the feature connector) and include this in the equation for pin 13 output enable.

Look what I found: https://github.com/rpocc/PALDump/tree/main/PA … base/VGA%20PEGA
It does what we need on pins 11 and 13, and /OE input is on pin 1. Which on this card is routed to pin 27 of the feature connector, which should be the switching signal for the buffer. So what are the chances this is the correct PAL data?

mkarcher wrote on Yesterday, 20:54:

That's not completely correct. The PAL should implement a gated pass-through. The PAL needs to receive the "/INTERNAL" signal from the EGA card

Yes, but then again if you don't plan on using the feature connector with external modules bypassing the built-in output driver, do you actually care? The wire works, why complicate things. But anyway take a look at the PAL dump I mentioned.

butjer1010 wrote on Yesterday, 20:09:

I have few spare 244 and 245, but i'm afraid i don't understand the "procedure" right :) I would be very grateful if You can say […]
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mkarcher wrote on Yesterday, 19:34:

A better solution than just bridging pin 24 to pin 30 and exposing the connection to the PEGA2A chip would be to add a non-inverting buffer chip at that location. You have the input to that buffer on pin 24, the output of the buffer needs to be connected to pin 30, and if you want to be fully EGA compatible, accepting all kind of hardware connected to the feature connector, you should take an active-low chip enable signal from pin 27 of the feature connector. +5V/GND can also be tapped from the feature connector, GND is at pin 31 and +5V is at pin 32. Suitable TTL chips that can use this signal to substitute the PAL driving the HSYNC signal are 74LS125, 74LS244 or 74LS245. All of these chips are non-inverting drivers with an active-low chip enable signal.

I have few spare 244 and 245, but i'm afraid i don't understand the "procedure" right 😀
I would be very grateful if You can say "on my language",.... if there is a simple solution like solder LS244 pin xx to feature port pin xx,....
If not, i owe You a lot already (and to the other guys here) for fixing this card for me !!!!

OK, if you use a 74LS244, you would need to connect

• +5V to pin 20 (for example taken from pin 20 of the PAL or pin 32 of the feature connector)
• GND to pin 10 (for example taken from pin 10 of the PAL or pin 31 of the feature connector)
• PEGA HSYNC (for example taken from pin 11 of the PAL or pin 24 of the feature connector) to any of the "low" input pins (2, 4, 5 or 😎, or any of the "high" input pins (11, 13, 15, 17).
• Monitor HSYNC (for example taken from 13 of the PAL or pin 30 of the feature connector) to the corresponding output pin. For the low input pins, 2 corresponds to 18, 4 corresponds to 16, 6 to 14 and 8 to 12. For the high input pins, 11 correspons to 9, 13 to 7, 15 to 5 and 17 to 3.
• /INTENAL (for example taken from pin 1 of the PAL or pin 27 of the feature connector) to pin 1 if you used a low input pin or pin 19 if you used a high input pin.

While it is not "good style", you can leave all the other input pins (you only need to use one of them) open on 74LS244 chips. You can't do that on 74HC244, though! It's a matter of taste whether you use a 74LS244 chip you already have, or you obtain a small single-gate SMD buffer chip. My personal approach would be to piggy-back the 74LS244 on the broken PAL, and

• solder the supply pins 10 and 20 of the 74LS244 directly to the corresponding PAL pins.
• decide to use a low input pin, so I can use /INTERNAL from pin 1 of the PAL, and solder pin 1 of the 74LS244
• cut pin 13 of the PAL (as it seems to be broken anyway), and connect pin 12 of the 74LS244 to the socket connection where pin 13 used to be. As pin 13 is an input pin of the 74LS244, you can connect pin 12 of the 74LS244 to pin 13 without any harm, and then solder the pin you cut from the PAL to extend pin 13 of the 74LS244 so it reaches the socket.
• run a bodge wire from pin 11 of the PAL to pin 8 of the 74LS244.
• connect pin 19 of the 74LS244 to pin 20 of the 74LS244. Do not connect it to pin 19 of the PAL. This disables half of the 74LS244. You might want to cut pin 19 short, so it can't touch pin 19 of the PAL.
• for making it mechanically more stable: solder pins 2 to 7 and pin 9 from the 74LS244 to the corresponding PAL pins. These 74LS244 pins are either input pins or disabled output pins, so that soldering doesn't hurt electrically
• also solder the "high input" pins 11, 15 and 17 to the PAL for added mechanical stability of the sandwich. Connecting pin 11 of the 74LS244 to pin 11 of the PAL means that the bodge wire from pin 11 to pin 8 of the 74LS244 can be run just on the 74LS244.
• do not connect pins pins 14, 16, 18. If you do not intend to re-use the 74LS244 later for a different purpose, cut them to avoid accidental connections.

There are obviously many other ways to do it, like building an adapter PCB for the feature connector or mounting an SMD chip on the solder side of the card.

Deunan wrote on Yesterday, 20:59:

Look what I found: https://github.com/rpocc/PALDump/tree/main/PA … base/VGA%20PEGA
It does what we need on pins 11 and 13, and /OE input is on pin 1. Which on this card is routed to pin 27 of the feature connector, which should be the switching signal for the buffer. So what are the chances this is the correct PAL data?

EXCELLENT find! Thank you for posting the link! This allowed me to consider the fact that /INTERNAL is on pin 1.

Deunan wrote on Yesterday, 21:01:

Yes, but then again if you don't plan on using the feature connector with external modules bypassing the built-in output driver, do you actually care? The wire works, why complicate things.

My thought was if we were going to clone the PAL anyway, adding the output enable statement to the equations would not add significant complication and restore the card to pristine condition.

butjer1010 wrote on Yesterday, 20:18:

I will try to read it, but does this chip exist in "database" of T48?
EDIT: no it does not 🙁

So I've been looking at it, and it seems rather safe to try. You will need a GAL16V8 PLD chip to program, it should be supported by T48. At least Atmel/Microchip ATF16V8B is supported. Preferably the BQ version as it consumes less power but B is good enought too.

Get the JED file from this page: https://github.com/rpocc/PALDump/tree/main/PA … base/VGA%20PEGA
Write it to the PLD chip, try the chip in place of the damaged PAL you have. If you get beeps or no picture then abort the test. But maybe it will work - I'm hoping there were some common ideas between some of these cards and therefore the PAL pinout is the same as yours.