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Lets make new M919 Cache sticks?

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Reply 160 of 161, by bertrammatrix

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feipoa wrote on Yesterday, 12:54:
The issue with Cyrix 5x86-120 chips and the 1024K module have been resolved. It seems that IBM 5x86c-100 chips soldered onto Th […]
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The issue with Cyrix 5x86-120 chips and the 1024K module have been resolved. It seems that IBM 5x86c-100 chips soldered onto Thinkpad interposers are not well liked by the M919. Switching to some other interposers resolved the issues at 120 MHz with 1024K cache. This is odd because every other socket 3 motherboard I tested worked well with the Thinkpad interposers.

I was able to achieve a stable M919 with 1024K and Cx5x86-120 MHz with 2-1-2 and 0/0 ws. I used 8 ns SRAM (TSOP) and 50 ns EDO (TSOP).

Note that if you need to use 1/0 ws with EDO, you can get slightly better performance if you have some FPM that runs with 1/0 ws. For example, on the M919, and (I think) MB-8433UUD when running an Am5x86-180, Cachechk v7 as follows:

EDO 0/0 ws --- memory read speed = 66.8 mb/s
FPM 1/0 ws --- memory read speed = 55.4 mb/s
EDO 1/0 ws --- memory read speed = 52.6 mb/s

And when running a Cx5x86-120, Cachechk v7 as follows:

EDO 0/0 ws --- memory read speed = 55.2 mb/s
FPM 0/0 ws --- memory read speed = 55.2 mb/s
FPM 1/0 ws --- memory read speed = 43.9 mb/s
EDO 1/0 ws --- memory read speed = 41.3 mb/s

Very, very impressive, I didn't think anyone would get one to run at 2-1-2 at 60mhz. Once again, you did it 😎

Was this with one of the latest s1R3 qfp CPUs or one of the older ones you had, or does the revision seem to affect the capability to run the tight timings at all? Did you also try with a regular IBM pga chip?

The 8ns sram must be giving you an extra edge here, especially in the tag

Is it windows stable is the next question 😀

Reply 161 of 161, by feipoa

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I was testing the Cyrix at 3x40, not 2x60. Is 2x60 what you are after on the M919? I doubt I will get 2-1-2 at 2x60 on the Cyrix, but will try. Cyrix at 3x40, 2-1-2, 0/0 ws, 1024K was stable in Win95c once I used the Chinese interposers.

8ns L2 and 50 ns TSOPs are the best combination so far. I'm using 64 MB modules. With tight timings, cannot go to 128 MB even if it is 50 ns and TSOP. 60 ns TSOP Samsung doesn't cut it for the fringe cases.

I only have S0R5 on the Thinkpad interposers, so I cannot say whether it was S0R5 in connection with the Thinkpad interposers that the M919 doesn't favour. I have, both, S0R5 and S1R3 on the Chinese generic interposers and they run fine on the M919.

I played around with my four S1R3 QFP CPUs. I'd probably start a new thread if I get some success. So far, one of the CPUs stands out at 150 MHz on the M919, but I am getting the feeling that the M919 isn't the best board for these tests. I will switch to the UUD, M918, or LSD shortly. The S1R3 chips don't like high voltages. At 150 Mhz, you cannot go above 3.8 V, and cannot really go below 3.65V. There's a really narrow sweet spot, at least on the M919. All 4 chips turn on at 150 MHz, and I suspect, in the least, they can do 2x66 (hopefully with all features enabled).

EDIT: I can confirm that a Cx5x86-120 at 2x60 with EDO needs 3-2-3, 1/0 to be fully stable. FPM also works with 3-2-3, 1/0 and has a slightly faster read speed of 62.1 MB/s vs. 58.6 MB/s for EDO.

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