Best guess on the last question is that slotocc is grounded by the terminator and some logic stops it.

For PCB impedance calculation you can use Saturn PCB Toolkit, it's freeware, you can select SE/Diff lines and various geometry configurations. AD also has buil-in impedance calculator in PCB stackup editor and goof tools for length control/matching.

arti9m wrote on 2024-12-11, 02:05:

A slight issue here is I am not a PCB or electronics engineer, just a hobbyist. I do understand the basics of signal transmission but I do not know how to properly calculate the impedance for 4-layer board, especially when most but not all of the inner layers are GND & Power planes.

Actually, you would prefer to have a full GND or power plane in the adjacent layer to all impedance controlled traces, preferably uninterrupted in the trace's entire length. The impedance controlled trace "sees" the adjacent plane as a capacitive reference to it self, which is why a 6-layer stackup with dedicated power/ground planes would really ease the layout work, albeit make it more costly.

I'm an electronics engineer, and have been doing PCB layouts for a living for ~15 years, and still don't understand it completely - there's definetely an element of black magic to it as well 🤣

But as a rule of thumb, uninterrupted power and/or ground planes adjacent to every impedance controlled trace, and width of tracks dependent on the actual spacing between layers. Also watch out not to have 2 equally spaced adjacent layers on each side of a trace, as it will then use both as a reference, thus making calculations go totally off 🤣

I think I would go with some stackup something like this if 6-layers is an option.

Signal Layer
prepreg
GND or PWR layer
prepreg
Signal Layer
|||||||| BASE FR4 ||||||||
Signal Layer
prepreg
GND or PWR layer
prepreg
Signal Layer

With prepreg layers of equal thickness, thus having pairs of layers using each plane as a reference.

On the other hand - if you have a working prototype with 4 layers, it's probably not that bad 😎

Found these 2 NOS sockets yesterday ... I'd really like a couple of slotkets now 😎

H3nrik V! wrote on 2024-12-11, 07:24:

Actually, you would prefer to have a full GND or power plane in the adjacent layer to all impedance controlled traces, preferabl […]
Show full quote

arti9m wrote on 2024-12-11, 02:05:

A slight issue here is I am not a PCB or electronics engineer, just a hobbyist. I do understand the basics of signal transmission but I do not know how to properly calculate the impedance for 4-layer board, especially when most but not all of the inner layers are GND & Power planes.

Actually, you would prefer to have a full GND or power plane in the adjacent layer to all impedance controlled traces, preferably uninterrupted in the trace's entire length. The impedance controlled trace "sees" the adjacent plane as a capacitive reference to it self, which is why a 6-layer stackup with dedicated power/ground planes would really ease the layout work, albeit make it more costly.

I'm an electronics engineer, and have been doing PCB layouts for a living for ~15 years, and still don't understand it completely - there's definetely an element of black magic to it as well 🤣

But as a rule of thumb, uninterrupted power and/or ground planes adjacent to every impedance controlled trace, and width of tracks dependent on the actual spacing between layers. Also watch out not to have 2 equally spaced adjacent layers on each side of a trace, as it will then use both as a reference, thus making calculations go totally off 🤣

I think I would go with some stackup something like this if 6-layers is an option.

Signal Layer
prepreg
GND or PWR layer
prepreg
Signal Layer
|||||||| BASE FR4 ||||||||
Signal Layer
prepreg
GND or PWR layer
prepreg
Signal Layer

With prepreg layers of equal thickness, thus having pairs of layers using each plane as a reference.

On the other hand - if you have a working prototype with 4 layers, it's probably not that bad 😎

Why don't the 2 middle signals interfere? Is the base fr4 special?

myne wrote on 2024-12-11, 07:59:

H3nrik V! wrote on 2024-12-11, 07:24:

Actually, you would prefer to have a full GND or power plane in the adjacent layer to all impedance controlled traces, preferabl […]
Show full quote

arti9m wrote on 2024-12-11, 02:05:

A slight issue here is I am not a PCB or electronics engineer, just a hobbyist. I do understand the basics of signal transmission but I do not know how to properly calculate the impedance for 4-layer board, especially when most but not all of the inner layers are GND & Power planes.

Actually, you would prefer to have a full GND or power plane in the adjacent layer to all impedance controlled traces, preferably uninterrupted in the trace's entire length. The impedance controlled trace "sees" the adjacent plane as a capacitive reference to it self, which is why a 6-layer stackup with dedicated power/ground planes would really ease the layout work, albeit make it more costly.

I'm an electronics engineer, and have been doing PCB layouts for a living for ~15 years, and still don't understand it completely - there's definetely an element of black magic to it as well 🤣

But as a rule of thumb, uninterrupted power and/or ground planes adjacent to every impedance controlled trace, and width of tracks dependent on the actual spacing between layers. Also watch out not to have 2 equally spaced adjacent layers on each side of a trace, as it will then use both as a reference, thus making calculations go totally off 🤣

I think I would go with some stackup something like this if 6-layers is an option.

Signal Layer
prepreg
GND or PWR layer
prepreg
Signal Layer
|||||||| BASE FR4 ||||||||
Signal Layer
prepreg
GND or PWR layer
prepreg
Signal Layer

With prepreg layers of equal thickness, thus having pairs of layers using each plane as a reference.

On the other hand - if you have a working prototype with 4 layers, it's probably not that bad 😎

Why don't the 2 middle signals interfere? Is the base fr4 special?

No, but I suggested FR4 as that being the core of the PCB, being way thicker than the prepreg layers (typically), making the cross-talk practically negilble. I see though, that a thick middle layer of prepreg is also suggested some places, with a distributed core (FR4) elsewhere in the stackup. Again, the above mentioned are my preferences, it seems that a center prepreg layer is actually often used, with FR4 (or other core) in 2 layers elsewhere in the stackup. While having other advantages, it's a big drawback IMO that not all layers have the same distance to planes.

Or maybe one should look into this: https://www.allpcb.com/6_layer_pcb.html

As I see, my proposed stackup is the "better" solution rather than the "best" (be it prepreg or core material is less than important, though, as long as dielectric constants and thicknesses are known). As I see it, in the "best" stackup I would believe that only the outermost layers should be used for impedance controlled traces.

Here are variants of JLC https://jlcpcb.com/impedance
I used JLC06161H-3313 Stackup if I remember well.

I think use of uncut whole gnd/pwr planes is more important than precise Z tunning...

RayeR wrote on 2024-12-11, 14:08:

Here are variants of JLC https://jlcpcb.com/impedance
I used JLC06161H-3313 Stackup if I remember well.

I think use of uncut whole gnd/pwr planes is more important than precise Z tunning...

Absolutely, uncut planes are of utmost importance, as every interruption of the reference layer results in a change in impedance ...

myne wrote on 2024-12-11, 07:59:

Why don't the 2 middle signals interfere? Is the base fr4 special?

Thickness. Ground plane between layers is good, distance is even better (as long as both layers are close to their own ground planes).

So eh.. A certain somebody PMed me asking for gerbers, but for the first time ever I haven't figured out how to reply 😒
Must be getting old 😁

Anyways, here are pre-production gerbers (checked & modified by NextPCB). Use at your own risk.
I still haven't tested it for stability because honestly I'm not too interested in this revision since it doesn't work in dual setup.
You absolutely must use thick inner layers (prefereably 2oz) for adequate power delivery.

Final reason for failing to work in dual CPU setup is thought to be excessive traces length. I didn't think about the traces leading to the intermediate CPU as "stubs", but I should've. Any traces that go off the main path (from chipset to last CPU) shouldn't be longer than 7.5cm in length, and my adapter traces are almost twice as much as that.

Also I am now left with ~30 boards that I don't really need. I'd just sell them for their production price but I most probably won't be able to mail them to you =(

oh the suspense is PALPABLE....

Oh wow.
Take the long way round 🤣

I assume you wanted lower profile?

Is the goal to get arti9m's design to the point where it can run dual CPUs (e.g. by trace length reduction, improved layer stacking, impedance matching, etc)? Is there someone still doing the BIOS mods to let PPRO chips run on PII/PIII slot 1 boards?

Did Mentat-vvo's design handle running dual CPUs on most motherboards? Are his PCB's no longer available?

First thing i'd do is rotate the socket.
Taller, but the traces will be a lot shorter.

Can't say for sure, but being from Vladivostok... Mentat is likely sanctioned

myne wrote on 2024-12-21, 04:35:

I assume you wanted lower profile?

Exactly. And I wanted the cooler to be positioned exactly in the middle. Had I placed the socket more to the right, the traces could've been considerably shorter.

feipoa wrote on 2024-12-21, 05:56:

Is the goal to get arti9m's design to the point where it can run dual CPUs (e.g. by trace length reduction, improved layer stacking, impedance matching, etc)? Is there someone still doing the BIOS mods to let PPRO chips run on PII/PIII slot 1 boards?

Forget about getting this to run 2 CPUs. Regarding BIOS support, AFAIK one of the forum members is working on patching AWARD BIOS patcher to include patches for PPro support. Other than that, there was a website with a lot of Asus BIOSes with PPro support. I can share my patched version of P2B-D(S) bios.

feipoa wrote on 2024-12-21, 05:56:

Did Mentat-vvo's design handle running dual CPUs on most motherboards? Are his PCB's no longer available?

Being a close Asus clone, that one indeed works. But it looks like shit suboptimal and has other issues. I have one of these adapters built and two more that I didn't bother to build yet.

myne wrote on 2024-12-21, 06:03:

First thing i'd do is rotate the socket. Taller, but the traces will be a lot shorter.

Absolutely. The next revision will be as fast (short) as possible signal-wise with no regards for the looks. It will also have proper ground/power planes and trace length matching.
I will be going for 8 layers with higher trace density (4 traces inbetween socket pins) which should make the traces as short as humanly possible.

Anybody with enough free time could really do it, all the docs for PPro/P2 are freely available on the webs.

Ah, rabbit holes.
So the gerbers looked a bit off in kicad.
So I figured I'd make my own slot 1 connector.
How hard can it be? There are specs and all.

Except Intel-Math(tm) doesn't math.

0.039" center-to-center ok cool. Easy.
Except what's 2.835" / 73?
Oh. A nice round number, of course.
0.0388356164383562

Probably translated from mm to mils to inches. 😒

myne wrote on 2024-12-21, 12:26:

So the gerbers looked a bit off in kicad. So I figured I'd make my own slot 1 connector. How hard can it be? There are specs an […]
Show full quote

So the gerbers looked a bit off in kicad.
So I figured I'd make my own slot 1 connector.
How hard can it be? There are specs and all.

Except Intel-Math(tm) doesn't math.

The gerbers are specifically for the production, made/edited by the factory. You won't be able to simply import them into most design programs. Same goes for gerbers I exported from SprintLayout.
Remember, gerbers are mostly just a couple of vector images stacked together. Almost no PCB software supports inverse shapes/polygons while there is such thing in gerber format.
Making this project in SprintLayout was a mistake in more ways than one 😁

I also had slight issues with Intel-Math, had to measure actual P2 CPUs a couple of times.
I can share SprintLayout source file (if you have that software or you're willing to find other means of using it).
Or I can create a PDF/image file with all the measurements of my adapter. It fits into the slot quite nicely and supports plastic "fixating bits" of some Slocket-370 adapters to hold the adapter in place (if you have original Slot-1 plastic holder on your mobo).

Oh, and maybe don't waste your time trying to "reverse-engineer" pins that are "reserved" on Socket-8. To my knowledge, there isn't a single special undocumented pin of interest on the Pentium Pro.
There is, however, a special pin on Asus S8-S1 adapter that connects "Upgrade" pin from Socket 8 to one "reserved" pin on Slot 1. It is most likely used on very early Asus Slot-1 440FX boards, or not used anywhere at all.

Which pin on the slot?
If it's B21, it's the dual processor pin.

BTW when talking about stubs on the SMP FSB... I remeber that I saw some dummy CPU boards (not sure if slot1 or PGA370) that was intended to be inserted in an empty CPU socket of dual CPU MB (if only one CPU used), probably containing some terminating resistors that lowered reflections from the unconnected bus stub ends.

I personally don't have any dual slot1 MB so I wouldn't worry that current adapter version doesn't support SMP. So I could use existing PCB but no idea about shipping from you to Czech Rep. I have problems with high taxes so maybe better to order myself in JLCPCB. I think about it, for me it's not high priority, I already have some S8 MBs, just think it would be a bit fun to push PPro harder in MB that allows higher FSB...