Yes, I remember there was many headaches with alternative chipsets like via and even worse ali. I also was tired by it a lot in PII/III era. Once I switched to intel chipset MB everything magically started to work as it should and I found a peace after endless count of sleepless nights... 😀

I read that. Its only on amd in rare circumstances.
Other bonus pci 2.2 for what it's worth. Maybe 66mhz with some tricks.

Are you redoing the whole thing from scratch?!
Are you fixing the net directives I screwed up?

Hmm, thats cool project
Bay the way, who will write the BIOS???

If a recreation uses the same list of parts that's already on an existing board : no need. Just use that.

If it was the crazed monster I just suggested...
Nooo fucking idea.

myne wrote on 2024-11-28, 15:10:

I read that. Its only on amd in rare circumstances.

Afaik on all via platforms, even Intel ones.

myne wrote on 2024-11-28, 15:10:

Other bonus pci 2.2 for what it's worth. Maybe 66mhz with some tricks.

Cant take advantage when main pci bridge in 440BX doesnt.

But since manufacturing full ATX pcb is super expensive it makes sense to make CPU AGP/1xPCI part, then separate PCI expander, then finally PCI-ISA bridge on PCI card.

myne wrote on 2024-11-28, 15:10:

Are you redoing the whole thing from scratch?!
Are you fixing the net directives I screwed up?

Not from scratch, just remolding to look 1:1 like original pdf. One page at a time. Havent stumbled into any major errors yet, just little insignificant details like for example making grounds Power Outputs. Im sure ill make some new errors too 😀

I just realized I dont even know the board this diagram is supposed to match :-] Is there one? In any case it will be a good resource for any potential future projects.

Might be this
https://theretroweb.com/motherboards/s/intel-se440bx-seattle

Or at least near enough.

Aka http://www.uktsupport.co.uk/pb/mb/870.htm
The superio and flash are basically the same...

myne wrote on 2024-11-28, 17:44:

Might be this
https://theretroweb.com/motherboards/s/intel-se440bx-seattle

Confirms 4 layer pcb. They cheated and used PLA (glue 2) 😀

I was googling images, saw this https://www.reddit.com/r/pcmasterrace/comment … seattle_2_slot/ and thumbnail

and just_recreated_the_intel_se440bx2_seattle_2_slot title made me go WTF someone beat us to it! haha

https://www.roberthancock.com/dell/xpsrproc.htm
Says the clockgens is this: https://www.alldatasheet.com/datasheet-pdf/pd … W48C101-01.html

Which doesn't do sdram clocks, meaning it must have a second clockgens just like the reference design.

Yeah I did see that at some point.

shevalier wrote on 2024-11-28, 16:01:

Hmm, thats cool project
Bay the way, who will write the BIOS???

There were efforts to get coreboot on ASUS P3B-F.

Maybe that can be used as a starting point for a new 440BX board design.

I can't check the project now, but putting in those big, old-fashioned inductors and capacitors in 2024 is a waste of time. You'll never find them

shevalier wrote on 2024-11-29, 05:42:

I can't check the project now, but putting in those big, old-fashioned inductors and capacitors in 2024 is a waste of time. You'll never find them

I think right now the goal is to make a board faithfully identical to the original one.

Of course, some components used back then have long become obsolete and superseded by modern ones over time.

Adjusting the board/footprints to make use of modern, available replacements can come after that.

Oh for sure.
As noted, there's a lot that has to be done before anyone can think about building anything.

This is just the start.

Get the reference design in and get a good feel for how it works.

The next step is deciding what to change. It looks like the main parts still exist in the wild but this reference design is very different to most boards made.
The easier route is to copy the components from an existing board so you can at least use a known working bios.

The superio specified seems to be rare. Can't boot without that. That will have to change to something more common like winbond. Then, which one? Maybe the bastardised via combo I mentioned a few posts ago?

The clockgens were generally ICS in most major brands. Eg the p3b was an ICS9250-08 which supported 133fsb and seems to be one of the best of the era. Availability is another question.
Can't boot without that.

The vrms were weak on this design and mosfets have come a long way.
Those all need redesigning - preferably for the full range of ppro>Tualatin voltages/watts AND ideally from the 12v line instead of 5v due to modern psus.
There are 3 main vrms. Core, vtt(signalling), sdram,

Then there's potentially agp, pci vrms. Isa can cope raw dogging off the psu.
Decisions have to be made on the agp and pci side. Is 3.3v agp and 5v pci too limiting? Does the builder want to support a universal 1.5&3.3 agp slot, and/or 3.3/5v pci?

Tualatins required pin mods to run on early boards. Those have to be checked and designed.

Then how crazy do you want to go with extras?
I personally have basically never used an lpt port. I couldn't care less if it was deleted. Same goes for serial but it might be necessary for debugging.
Improvements were made to both to consolidate 50 components into one IC. Is that available?
I do recognise that ide is practically unavailable, so a sata bridge chip would be ideal.
Which one? Just a regular sata slot or an m.2 sata too? 2 or all 4 ports?
Onboard lan? What's available? What meets compatibility requirements?
Onboard sound? What's available? What meets compatibility requirements?
How about a pcie Bridge option? It's getting hard to find some things for this era.

After all that, you still need to pick a board size, make everything fit, and design the trace layouts.

In many ways, this era was maxing signalling in ways we've bypassed now.
Pci is 32 individual traces running side-by-side and absolutely need to be the same length as best as possible. Each one is going to get interference.

The much, much faster pcie is less demanding because it uses multiple individual serial differential pairs operating as a network trunk. Differential pairs send opposite signals down 2 wires. Any interference applies to both in an opposing way, and can be fixed simply.
Eg if I send +3v and -3v down 2 wires, and interference adds 1v, you get +4v and -2v.
Because you know they're supposed to be identical, you can infer that the interference was +1v, so you can -1v from both and reconstruct the original signal. Pci can't do that.

Isa is practically bulletproof through sheer power and slowness, so pci is basically the slowest bus on the potential board and it's going to be challenging.
Fsb/ram is even harder.

Anyway...

Long, long way to go.

Do you intend to use a FPGA to reimplement the BX chipset?

If so, that would solve the 'original chips no longer being made' and 'what superio to use' questions. Assuming you use a fast enough, and cheap enough FPGA, you can have a single, readily available chip provide those functions.

The major parts appear to be available in large enough quantities either as new-old-stock or reclaimed.

So far I've seen: 440bx/gx, pii4x (southbridge), various winbond superios, many ICS clockgens, and all the slots/sockets listed for sale in various places.

That's everything that absolutely must exist.
Passive components are interchangeable, and vrms as stated would have to be designed anyway but aren't things an operating system would see. Bios.... To some extent. I wouldn't expect soft-voltages. Jumpers and/or vid select only.

Also... Pfgas are, as a rule, either not fast, or extremely expensive, and are extremely difficult to code up. One with around 400 pins, functionally copying the bx chipset down to the registers, coded by an amateur and running at 133mhz?
Pipedream.
The mista can barely do a 486sx and many, many more people, with far more relevant skills have worked on that.

Implementing standard common chipset in fast and expansive fpga doesn'tmake much sense. Coding tons of vhdl is not easy task either...
COM and LPT ports are very usefull to connect with old hardware and various elctronic tools. For this reason I still use GB MB in signature that has LPT and COM, e.g. using it for chip programmers, etc. And it does cost you nothing because every superIO chip of that era contained COM, LPT, FDC so you just need to route wires on a header + add some resistors around, for RS232 also level shifters...

There were some quirks with 440BX from what I could remember...

- Socket 370 versions
There were 3 different versions of Socket 370 (Mendocino, Coppermine and Tualatin). The Tualatin one introduced some changes to the socket requiring the use of an adapter.
Ideally the latter two should be properly supported in the final design. The former one was during the period of Pentium II (Slot 1).
And there's the question with VIA CPUs using the same socket. On a VIA chipset board (CUV4X) I could use a 1.2A (Nehemiah) without the need of an adapter, whereas I do need one for a Tualatin there.

- FSB 133 questions
I think this is more about clock generators eventually. Back then my own 440BX (Slot 1) board only supported 133/44, but there were boards that could do 133/33.
However, there were issues about AGP that running FSB133 would make it run overclocked at 89MHz instead of 66MHz due to not having a proper 1:2 divider. But from a few previous posts, some clock generator models can be made to generate correct clock for the AGP bus, working it around.

- Hard disk size limit
Pretty much all 440BX/PIIX4 boards I know of do not support 48-bit LBA which hard disks larger than 128GiB require. I wonder if this is simply a BIOS issue, or a limitation from PIIX4 itself.

LSS10999 wrote on 2024-11-30, 03:23:

Pretty much all 440BX/PIIX4 boards I know of do not support 48-bit LBA which hard disks larger than 128GiB require. I wonder if this is simply a BIOS issue, or a limitation from PIIX4 itself.

This is BIOS limitation, on low-level IDE port access proper LBA48 ATA commands can be used. So you just need a driver and don't rely on BIOS INT13h services.

pages 9 10 11 DIMM socket and DIMM socket symbol done

RayeR wrote on 2024-11-30, 04:43:

This is BIOS limitation, on low-level IDE port access proper LBA48 ATA commands can be used. So you just need a driver and don't rely on BIOS INT13h services.

I always assumed Hardware DMA IDE controller like piix4e would be able to program sector numbers automagically, but apparently https://www.microsoft.com/en-us/research/publ … e-intel-piix4e/ https://www.microsoft.com/en-us/research/wp-c … ance_report.pdf you still have to program everything with manual I/O and only the DMA part is automated thru descriptor tables
"DMA Setup / Cleanup
In between each disk request, a series of PIO’s is issued by the host (driver) in order to check the status of
the finished request and set up the next request. "

myne wrote on 2024-11-29, 08:04:

Also... Pfgas are, as a rule, either not fast, or extremely expensive, and are extremely difficult to code up. One with around 400 pins, functionally copying the bx chipset down to the registers, coded by an amateur and running at 133mhz? Pipedream.
The mista can barely do a 486sx and many, many more people, with far more relevant skills have worked on that.

FPGAs are extremely fast, not always expensive, and easy to code once you wrap your head around the fact you are defining hardware and not writing software. Mister emulates complex CPU, PCI bridge is much easier. Its like comparing brain vs arm transplant. P2-3 run in the 7-9million transistors, Chipsets are below 1 mil. PIIX4E is even simpler (maybe 200K transistors without PCI and USB).

Thoughts on agp.
BX is 2x 3.3v.
In my experience, bus speed wasn't a huge problem with enough vram.
What is a problem is the voltage. Many cards are universal, but a few wont tolerate 3.3v. All 4x and 8x cards work at 1.5v.
Looks like that's not too hard by using a vrm on the vddq pins, and logic level shifters for the bus.
The last 2 reserved pins in agp1 were later used to say 1.5v only but grounding it.
I assume a transistor that grounds via that pin is enough to switch it.

The ti LSF0102 look right for the bus logic.
I have no idea though.

Since I know f-all, any risks with that logic?

The agp2 design guide is fairly easy to find, but the 3 is a impossible. Some interesting stuff in there. Importantly signal lengths and tolerances. They don't need to be matched (within x)

https://www.playtool.com/pages/agpcompat/agp.html
http://esd.cs.ucr.edu/webres/agp20.pdf
https://www.ti.com/product/LSF0102

Very random thought on the p4/pentium m bus.
It looks like it's gtl the same as PPro - p3, but like agp4x it sends 4 bits per fsb clock.
Ie, 100 clock, 4 bits =400fsb.
None of the 440xx/8xx chipsets could do that obviously, but what if...
You put a 4:1 clock divider into the Pentium m clock reference giving it a 25mhz clock, and 100 to the bx chipset?

Assuming they were synced properly, it just crazy enough that it might work. ;p
Naturally, the chip's multiplier limits would result in a 1/4 top speed.

But it'd be kinda crazy if that's all it was.

Stupid amount of work to find out though - and be left with a chip slower than most p3s 🤣

Pentium M 765 =21x multipler. 21x25=525.
Absolute wildly optimistic best case, overclock fsb to 166 /4 x21=871. Probably why no one bothered even if they had the same thoughts.