RayeR wrote on 2023-10-24, 12:42:
Exceeding the absolute max. rating is not good idea generally, esp. for long run. But for some retroplaying it probaby would not degrade too fast. A tiny SMPS would be possible, modern components like used in smartphones can easily fit on top side under heatsing not exceesing 0.8-1mm height. Also for perfect match there should be some voltage level translators on each IO pin (probably it's not 3.3V tolerant) but when VIO and logic high difference would be below 0.5V it would be ok. I didn't pay enough attention on this in datasheet, now it's too late to add it in design. But it's more just for fun project than daily workhorse PC so I don't care too much. Just to notice others there exist such issue...
Then also the power dissipation would be higher than I read from DS, maybe close to non-mobile MMX that was about 17w...
Basically everyone playing with tillamooks is doing 3.3v i/o and we aren’t seeing any failures
The p55 had 3.3vio, (on a larger process granted) but it came with chips rated down to 2.45 core and 3.3v io
Two possibilities: the tillamook is 3.3vio tolerant and was rated to 2.5vio for motherboard/thermal envelope reasons
Or two it is being over volted but we aren’t seeing any failures
In either case, a problem doesn’t seem to exist.
I would like to know which one, but I don’t think we would ever know for sure unless we got a intel engineer in here.
Some motherboards can do 3.5 vio, someone could run a tillamook on that for a while to see how close we are to failure mode. 🤷♂️ (for science)
Btw, my s5/7/ss7 voltage interceptor interposer is designed to allow vio to be divorced from motherboard vio if you set it up for that. If you wanted to do experiments