1- All IMUL8/16/32 instructions.
2- DIVDX W regarding #DE(not faulting).
3- DIVEDX W/DIVEDX D regarding #DE(not faulting).
4- DIVAX W regarding #DE(not faulting).
5- DIVEAX D regarding #DE(not faulting).
6- IDIVDL B not always faulting #DE.
7- IDIVEDX D not always faulting #DE.
8- IDIVEDX D EAX = 80000001 EDX = FFFFFFFF PS = 0000 wrong result?
9etc.
10- Shift/rotate carry flags problems? :
11- SALr B/W/D flags problems?
12- SHRr B/W/D flags problems?
13- ROLr B/W/D flags problems?
14- RORr B/W/D flags problems?
15- RCLr B/W/D problems?
16- RCRr B/W/D problems?

1temp2.val64 = (uint_64)immb; //Read unsigned parameter!
2if (temp2.val64&0x80ULL) temp2.val64 |= 0xFFFFFFFFFFFFFF00ULL; //Sign extend to 64 bits!

1temp2.val64 = (int_8)immb;

1temp3.val64s = temp1.val64s * temp2.val64s;

1/*
2
3checkSignedOverflow: Checks if a signed overflow occurs trying to store the data.
4unsignedval: The unsigned, positive value
5calculatedbits: The amount of bits that's stored in unsignedval.
6bits: The amount of bits to store in.
7convertedtopositive: The unsignedval is a positive conversion from a negative result, so needs to be converted back.
8
9*/
10
11//Based on http://www.ragestorm.net/blogs/?p=34
12
13byte checkSignedOverflow(uint_64 unsignedval, byte calculatedbits, byte bits, byte convertedtopositive)
14{
15	uint_64 maxpositive,maxbit,errorrange;
16	if (convertedtopositive) unsignedval = (~unsignedval)+1; //Convert to negative, if needed!
17	maxpositive = ((1ULL<<(bits-1))-1); //Maximum positive value we can have!
18	maxbit = (1ULL<<(bits-1)); //The highest value we cannot set!
19	errorrange = ((1ULL<<bits)-1)-maxpositive; //Lower roof of invalid range!
20	if (unlikely((unsignedval>maxpositive) && ((unsignedval<maxbit)||(unsignedval>errorrange)))) //Signed underflow/overflow on unsinged conversion?
21	{
22		return 1; //Underflow/overflow detected!
23	}
24	return 0; //OK!
25}

1//Universal DIV instruction for x86 DIV instructions!
2/*
3
4Parameters:
5	val: The value to divide
6	divisor: The value to divide by
7	quotient: Quotient result container
8	remainder: Remainder result container
9	error: 1 on error(DIV0), 0 when valid.
10	resultbits: The amount of bits the result contains(16 or 8 on 8086) of quotient and remainder.
11	SHLcycle: The amount of cycles for each SHL.
12	ADDSUBcycle: The amount of cycles for ADD&SUB instruction to execute.
13	issigned: Signed division?
14	quotientnegative: Quotient is signed negative result?
15	remaindernegative: Remainder is signed negative result?
16
17*/
18void CPU80386_internal_DIV(uint_64 val, uint_32 divisor, uint_32 *quotient, uint_32 *remainder, byte *error, byte resultbits, byte SHLcycle, byte ADDSUBcycle, byte *applycycles, byte issigned, byte quotientnegative, byte remaindernegative)
19{
20	uint_64 temp, temp2, currentquotient; //Remaining value and current divisor!
21	uint_64 resultquotient;
22	byte shift; //The shift to apply! No match on 0 shift is done!
23	temp = val; //Load the value to divide!
24	*applycycles = 1; //Default: apply the cycles normally!
25	if (divisor==0) //Not able to divide?
26	{
27		*quotient = 0;
28		*remainder = temp; //Unable to comply!
29		*error = 1; //Divide by 0 error!
30		return; //Abort: division by 0!
31	}
32
33	if (CPU_apply286cycles()) /* No 80286+ cycles instead? */
34	{
35		SHLcycle = ADDSUBcycle = 0; //Don't apply the cycle counts for this instruction!
36		*applycycles = 0; //Don't apply the cycles anymore!
37	}
38
39	temp = val; //Load the remainder to use!
40	resultquotient = 0; //Default: we have nothing after division! 
41	nextstep:
42	//First step: calculate shift so that (divisor<<shift)<=remainder and ((divisor<<(shift+1))>remainder)
43	temp2 = divisor; //Load the default divisor for x1!
44	if (temp2>temp) //Not enough to divide? We're done!
45	{
46		goto gotresult; //We've gotten a result!
47	}
48	currentquotient = 1; //We're starting with x1 factor!
49	for (shift=0;shift<(resultbits+1);++shift) //Check for the biggest factor to apply(we're going from bit 0 to maxbit)!
50	{
51		if ((temp2<=temp) && ((temp2<<1)>temp)) //Found our value to divide?
52		{
53			CPU[activeCPU].cycles_OP += SHLcycle; //We're taking 1 more SHL cycle for this!
54			break; //We've found our shift!
55		}
56		temp2 <<= 1; //Shift to the next position!
57		currentquotient <<= 1; //Shift to the next result!
58		CPU[activeCPU].cycles_OP += SHLcycle; //We're taking 1 SHL cycle for this! Assuming parallel shifting!
59	}
60	if (shift==(resultbits+1)) //We've overflown? We're too large to divide!

61	{
62		*error = 1; //Raise divide by 0 error due to overflow!
63		return; //Abort!
64	}
65	//Second step: substract divisor<<n from remainder and increase result with 1<<n.
66	temp -= temp2; //Substract divisor<<n from remainder!
67	resultquotient += currentquotient; //Increase result(divided value) with the found power of 2 (1<<n).
68	CPU[activeCPU].cycles_OP += ADDSUBcycle; //We're taking 1 substract and 1 addition cycle for this(ADD/SUB register take 3 cycles)!
69	goto nextstep; //Start the next step!
70	//Finished when remainder<divisor or remainder==0.
71	gotresult: //We've gotten a result!
72	if ((uint_64)temp>((1ULL<<resultbits)-1)) //Modulo overflow?
73	{
74		*error = 1; //Raise divide by 0 error due to overflow!
75		return; //Abort!		
76	}
77	if ((uint_64)resultquotient>((1ULL<<resultbits)-1)) //Quotient overflow?
78	{
79		*error = 1; //Raise divide by 0 error due to overflow!
80		return; //Abort!		
81	}
82	if (issigned) //Check for signed overflow as well?
83	{
84		/*
85		if (checkSignedOverflow((uint_64)temp,64,resultbits,remaindernegative))
86		{
87			*error = 1; //Raise divide by 0 error due to overflow!
88			return; //Abort!					
89		}
90		*/
91		if (checkSignedOverflow((uint_64)resultquotient,64,resultbits,quotientnegative))
92		{
93			*error = 1; //Raise divide by 0 error due to overflow!
94			return; //Abort!					
95		}
96	}
97	*quotient = resultquotient; //Quotient calculated!
98	*remainder = temp; //Give the modulo! The result is already calculated!
99	*error = 0; //We're having a valid result!
100}
101
102void CPU80386_internal_IDIV(uint_64 val, uint_32 divisor, uint_32 *quotient, uint_32 *remainder, byte *error, byte resultbits, byte SHLcycle, byte ADDSUBcycle, byte *applycycles)
103{
104	byte quotientnegative, remaindernegative; //To toggle the result and apply sign after and before?
105	quotientnegative = remaindernegative = 0; //Default: don't toggle the result not remainder!
106	if (((val>>31)!=(divisor>>15))) //Are we to change signs on the result? The result is negative instead! (We're a +/- or -/+ division)
107	{
108		quotientnegative = 1; //We're to toggle the result sign if not zero!
109	}
110	if (val&0x80000000) //Negative value to divide?
111	{
112		val = ((~val)+1); //Convert the negative value to be positive!
113		remaindernegative = 1; //We're to toggle the remainder is any, because the value to divide is negative!
114	}
115	if (divisor&0x8000) //Negative divisor? Convert to a positive divisor!
116	{
117		divisor = ((~divisor)+1); //Convert the divisor to be positive!
118	}
119	CPU80386_internal_DIV(val,divisor,quotient,remainder,error,resultbits,SHLcycle,ADDSUBcycle,applycycles,1,quotientnegative,remaindernegative); //Execute the division as an unsigned division!
120	if (*error==0) //No error has occurred? Do post-processing of the results!
121	{
122		if (quotientnegative) //The result is negative?
123		{
124			*quotient = (~*quotient)+1; //Apply the new sign to the result!
125		}
126		if (remaindernegative) //The remainder is negative?
127		{
128			*remainder = (~*remainder)+1; //Apply the new sign to the remainder!
129		}
130	}
131}

1//Universal DIV instruction for x86 DIV instructions!
2/*
3
4Parameters:
5	val: The value to divide
6	divisor: The value to divide by
7	quotient: Quotient result container
8	remainder: Remainder result container
9	error: 1 on error(DIV0), 0 when valid.
10	resultbits: The amount of bits the result contains(16 or 8 on 8086) of quotient and remainder.
11	SHLcycle: The amount of cycles for each SHL.
12	ADDSUBcycle: The amount of cycles for ADD&SUB instruction to execute.
13	issigned: Signed division?
14	quotientnegative: Quotient is signed negative result?
15	remaindernegative: Remainder is signed negative result?
16
17*/
18void CPU8086_internal_DIV(uint_32 val, word divisor, word *quotient, word *remainder, byte *error, byte resultbits, byte SHLcycle, byte ADDSUBcycle, byte *applycycles, byte issigned, byte quotientnegative, byte remaindernegative)
19{
20	uint_32 temp, temp2, currentquotient; //Remaining value and current divisor!
21	uint_32 resultquotient;
22	byte shift; //The shift to apply! No match on 0 shift is done!
23	temp = val; //Load the value to divide!
24	*applycycles = 1; //Default: apply the cycles normally!
25	if (divisor==0) //Not able to divide?
26	{
27		*quotient = 0;
28		*remainder = temp; //Unable to comply!
29		*error = 1; //Divide by 0 error!
30		return; //Abort: division by 0!
31	}
32
33	if (CPU_apply286cycles()) /* No 80286+ cycles instead? */
34	{
35		SHLcycle = ADDSUBcycle = 0; //Don't apply the cycle counts for this instruction!
36		*applycycles = 0; //Don't apply the cycles anymore!
37	}
38
39	temp = val; //Load the remainder to use!
40	resultquotient = 0; //Default: we have nothing after division! 
41	nextstep:
42	//First step: calculate shift so that (divisor<<shift)<=remainder and ((divisor<<(shift+1))>remainder)
43	temp2 = divisor; //Load the default divisor for x1!
44	if (temp2>temp) //Not enough to divide? We're done!
45	{
46		goto gotresult; //We've gotten a result!
47	}
48	currentquotient = 1; //We're starting with x1 factor!
49	for (shift=0;shift<(resultbits+1);++shift) //Check for the biggest factor to apply(we're going from bit 0 to maxbit)!
50	{
51		if ((temp2<=temp) && ((temp2<<1)>temp)) //Found our value to divide?
52		{
53			CPU[activeCPU].cycles_OP += SHLcycle; //We're taking 1 more SHL cycle for this!
54			break; //We've found our shift!
55		}
56		temp2 <<= 1; //Shift to the next position!
57		currentquotient <<= 1; //Shift to the next result!
58		CPU[activeCPU].cycles_OP += SHLcycle; //We're taking 1 SHL cycle for this! Assuming parallel shifting!
59	}
60	if (shift==(resultbits+1)) //We've overflown? We're too large to divide!

61	{
62		*error = 1; //Raise divide by 0 error due to overflow!
63		return; //Abort!
64	}
65	//Second step: substract divisor<<n from remainder and increase result with 1<<n.
66	temp -= temp2; //Substract divisor<<n from remainder!
67	resultquotient += currentquotient; //Increase result(divided value) with the found power of 2 (1<<n).
68	CPU[activeCPU].cycles_OP += ADDSUBcycle; //We're taking 1 substract and 1 addition cycle for this(ADD/SUB register take 3 cycles)!
69	goto nextstep; //Start the next step!
70	//Finished when remainder<divisor or remainder==0.
71	gotresult: //We've gotten a result!
72	if (temp>((1<<resultbits)-1)) //Modulo overflow?
73	{
74		*error = 1; //Raise divide by 0 error due to overflow!
75		return; //Abort!		
76	}
77	if (resultquotient>((1<<resultbits)-1)) //Quotient overflow?
78	{
79		*error = 1; //Raise divide by 0 error due to overflow!
80		return; //Abort!		
81	}
82	if (issigned) //Check for signed overflow as well?
83	{
84		/*
85		if (checkSignedOverflow(temp,32,resultbits,remaindernegative))
86		{
87			*error = 1; //Raise divide by 0 error due to overflow!
88			return; //Abort!					
89		}
90		*/
91		if (checkSignedOverflow(resultquotient,32,resultbits,quotientnegative))
92		{
93			*error = 1; //Raise divide by 0 error due to overflow!
94			return; //Abort!					
95		}
96	}
97	*quotient = resultquotient; //Quotient calculated!
98	*remainder = temp; //Give the modulo! The result is already calculated!
99	*error = 0; //We're having a valid result!
100}
101
102void CPU8086_internal_IDIV(uint_32 val, word divisor, word *quotient, word *remainder, byte *error, byte resultbits, byte SHLcycle, byte ADDSUBcycle, byte *applycycles)
103{
104	byte quotientnegative, remaindernegative; //To toggle the result and apply sign after and before?
105	quotientnegative = remaindernegative = 0; //Default: don't toggle the result not remainder!
106	if (((val>>31)!=(divisor>>15))) //Are we to change signs on the result? The result is negative instead! (We're a +/- or -/+ division)
107	{
108		quotientnegative = 1; //We're to toggle the result sign if not zero!
109	}
110	if (val&0x80000000) //Negative value to divide?
111	{
112		val = ((~val)+1); //Convert the negative value to be positive!
113		remaindernegative = 1; //We're to toggle the remainder is any, because the value to divide is negative!
114	}
115	if (divisor&0x8000) //Negative divisor? Convert to a positive divisor!
116	{
117		divisor = ((~divisor)+1); //Convert the divisor to be positive!
118	}
119	CPU8086_internal_DIV(val,divisor,quotient,remainder,error,resultbits,SHLcycle,ADDSUBcycle,applycycles,1,quotientnegative,remaindernegative); //Execute the division as an unsigned division!
120	if (*error==0) //No error has occurred? Do post-processing of the results!
121	{
122		if (quotientnegative) //The result is negative?
123		{
124			*quotient = (~*quotient)+1; //Apply the new sign to the result!
125		}
126		if (remaindernegative) //The remainder is negative?
127		{
128			*remainder = (~*remainder)+1; //Apply the new sign to the remainder!
129		}
130	}
131}

1	CPU8086_internal_DIV(REG_AL,data,&quotient,&remainder,&error,8,2,6,&applycycles,0,0,0);

1	CPU8086_internal_DIV(valdiv,divisor,&quotient,&remainder,&error,8,2,6,&applycycles,0,0,0); //Execute the unsigned division! 8-bits result and modulo!

1	valdivd = valdiv;
2	divisorw = divisor;
3	if (valdiv&0x8000) valdivd |= 0xFFFF0000; //Sign extend to 32-bits!
4	if (divisor&0x80) divisorw |= 0xFF00; //Sign extend to 16-bits!
5	CPU8086_internal_IDIV(valdivd,divisorw,&quotient,&remainder,&error,8,2,6,&applycycles); //Execute the unsigned division! 8-bits result and modulo!

1	CPU8086_internal_DIV(valdiv,divisor,&quotient,&remainder,&error,16,2,6,&applycycles,0,0,0); //Execute the unsigned division! 8-bits result and modulo!

1	CPU8086_internal_IDIV(valdiv,divisor,&quotient,&remainder,&error,16,2,6,&applycycles); //Execute the unsigned division! 8-bits result and modulo!

1	CPU80386_internal_DIV(valdiv,divisor,&quotient,&remainder,&error,32,2,6,&applycycles,0,0,0); //Execute the unsigned division! 8-bits result and modulo!

1	CPU80386_internal_IDIV(valdiv,divisor,&quotient,&remainder,&error,32,2,6,&applycycles); //Execute the unsigned division! 8-bits result and modulo!

1/*
2
3checkSignedOverflow: Checks if a signed overflow occurs trying to store the data.
4unsignedval: The unsigned, positive value
5calculatedbits: The amount of bits that's stored in unsignedval.
6bits: The amount of bits to store in.
7convertedtopositive: The unsignedval is a positive conversion from a negative result, so needs to be converted back.
8
9*/
10
11//Based on http://www.ragestorm.net/blogs/?p=34
12
13byte checkSignedOverflow(uint_64 unsignedval, byte calculatedbits, byte bits, byte convertedtopositive)
14{
15	uint_64 maxpositive,maxnegative;
16	maxpositive = ((1ULL<<(bits-1))-1); //Maximum positive value we can have!
17	maxnegative = (1ULL<<(bits-1)); //The highest value we cannot set and get past when negative!
18	if (unlikely(((unsignedval>maxpositive) && (convertedtopositive==0)) && ((unsignedval>maxnegative) && (convertedtopositive)))) //Signed underflow/overflow on unsinged conversion?
19	{
20		return 1; //Underflow/overflow detected!
21	}
22	return 0; //OK!
23}

1IDIVDL B EAX=00000080 EDX=00000001 PS=0000 #DE EAX=00000080 EDX=00000001 PS=0000 

1IDIVDL B EAX=00000080 EDX=00000001 PS=0000 EAX=00000080 EDX=00000001 PS=0000 

1/*
2
3checkSignedOverflow: Checks if a signed overflow occurs trying to store the data.
4unsignedval: The unsigned, positive value
5calculatedbits: The amount of bits that's stored in unsignedval.
6bits: The amount of bits to store in.
7convertedtopositive: The unsignedval is a positive conversion from a negative result, so needs to be converted back.
8
9*/
10
11//Based on http://www.ragestorm.net/blogs/?p=34
12
13byte checkSignedOverflow(uint_64 unsignedval, byte calculatedbits, byte bits, byte convertedtopositive)
14{
15	uint_64 maxpositive,maxnegative;
16	maxpositive = ((1ULL<<(bits-1))-1); //Maximum positive value we can have!
17	maxnegative = (1ULL<<(bits-1)); //The highest value we cannot set and get past when negative!
18	if (unlikely(((unsignedval>maxpositive) && (convertedtopositive==0)) || ((unsignedval>maxnegative) && (convertedtopositive)))) //Signed underflow/overflow on unsinged conversion?
19	{
20		return 1; //Underflow/overflow detected!
21	}
22	return 0; //OK!
23}

1//Universal DIV instruction for x86 DIV instructions!
2/*
3
4Parameters:
5	val: The value to divide
6	divisor: The value to divide by
7	quotient: Quotient result container
8	remainder: Remainder result container
9	error: 1 on error(DIV0), 0 when valid.
10	resultbits: The amount of bits the result contains(16 or 8 on 8086) of quotient and remainder.
11	SHLcycle: The amount of cycles for each SHL.
12	ADDSUBcycle: The amount of cycles for ADD&SUB instruction to execute.
13	issigned: Signed division?
14	quotientnegative: Quotient is signed negative result?
15	remaindernegative: Remainder is signed negative result?
16
17*/
18void CPU8086_internal_DIV(uint_32 val, word divisor, word *quotient, word *remainder, byte *error, byte resultbits, byte SHLcycle, byte ADDSUBcycle, byte *applycycles, byte issigned, byte quotientnegative, byte remaindernegative)
19{
20	uint_32 temp, temp2, currentquotient; //Remaining value and current divisor!
21	uint_32 resultquotient;
22	byte shift; //The shift to apply! No match on 0 shift is done!
23	temp = val; //Load the value to divide!
24	*applycycles = 1; //Default: apply the cycles normally!
25	if (divisor==0) //Not able to divide?
26	{
27		*quotient = 0;
28		*remainder = temp; //Unable to comply!
29		*error = 1; //Divide by 0 error!
30		return; //Abort: division by 0!
31	}
32
33	if (CPU_apply286cycles()) /* No 80286+ cycles instead? */
34	{
35		SHLcycle = ADDSUBcycle = 0; //Don't apply the cycle counts for this instruction!
36		*applycycles = 0; //Don't apply the cycles anymore!
37	}
38
39	temp = val; //Load the remainder to use!
40	resultquotient = 0; //Default: we have nothing after division! 
41	nextstep:
42	//First step: calculate shift so that (divisor<<shift)<=remainder and ((divisor<<(shift+1))>remainder)
43	temp2 = divisor; //Load the default divisor for x1!
44	if (temp2>temp) //Not enough to divide? We're done!
45	{
46		goto gotresult; //We've gotten a result!
47	}
48	currentquotient = 1; //We're starting with x1 factor!
49	for (shift=0;shift<(resultbits+1);++shift) //Check for the biggest factor to apply(we're going from bit 0 to maxbit)!
50	{
51		if ((temp2<=temp) && ((temp2<<1)>temp)) //Found our value to divide?
52		{
53			CPU[activeCPU].cycles_OP += SHLcycle; //We're taking 1 more SHL cycle for this!
54			break; //We've found our shift!
55		}
56		temp2 <<= 1; //Shift to the next position!
57		currentquotient <<= 1; //Shift to the next result!
58		CPU[activeCPU].cycles_OP += SHLcycle; //We're taking 1 SHL cycle for this! Assuming parallel shifting!
59	}
60	if (shift==(resultbits+1)) //We've overflown? We're too large to divide!

61	{
62		*error = 1; //Raise divide by 0 error due to overflow!
63		return; //Abort!
64	}
65	//Second step: substract divisor<<n from remainder and increase result with 1<<n.
66	temp -= temp2; //Substract divisor<<n from remainder!
67	resultquotient += currentquotient; //Increase result(divided value) with the found power of 2 (1<<n).
68	CPU[activeCPU].cycles_OP += ADDSUBcycle; //We're taking 1 substract and 1 addition cycle for this(ADD/SUB register take 3 cycles)!
69	goto nextstep; //Start the next step!
70	//Finished when remainder<divisor or remainder==0.
71	gotresult: //We've gotten a result!
72	if (temp>((1<<resultbits)-1)) //Modulo overflow?
73	{
74		*error = 1; //Raise divide by 0 error due to overflow!
75		return; //Abort!		
76	}
77	if (resultquotient>((1<<resultbits)-1)) //Quotient overflow?
78	{
79		*error = 1; //Raise divide by 0 error due to overflow!
80		return; //Abort!		
81	}
82	if (issigned) //Check for signed overflow as well?
83	{
84		/*
85		if (checkSignedOverflow(temp,32,resultbits,remaindernegative))
86		{
87			*error = 1; //Raise divide by 0 error due to overflow!
88			return; //Abort!
89		}
90		*/
91		if (checkSignedOverflow(resultquotient,32,resultbits,quotientnegative))
92		{
93			*error = 1; //Raise divide by 0 error due to overflow!
94			return; //Abort!
95		}
96	}
97	*quotient = resultquotient; //Quotient calculated!
98	*remainder = temp; //Give the modulo! The result is already calculated!
99	*error = 0; //We're having a valid result!
100}
101
102void CPU8086_internal_IDIV(uint_32 val, word divisor, word *quotient, word *remainder, byte *error, byte resultbits, byte SHLcycle, byte ADDSUBcycle, byte *applycycles)
103{
104	byte quotientnegative, remaindernegative; //To toggle the result and apply sign after and before?
105	quotientnegative = remaindernegative = 0; //Default: don't toggle the result not remainder!
106	if (((val>>31)!=(divisor>>15))) //Are we to change signs on the result? The result is negative instead! (We're a +/- or -/+ division)
107	{
108		quotientnegative = 1; //We're to toggle the result sign if not zero!
109	}
110	if (val&0x80000000) //Negative value to divide?
111	{
112		val = ((~val)+1); //Convert the negative value to be positive!
113		remaindernegative = 1; //We're to toggle the remainder is any, because the value to divide is negative!
114	}
115	if (divisor&0x8000) //Negative divisor? Convert to a positive divisor!
116	{
117		divisor = ((~divisor)+1); //Convert the divisor to be positive!
118	}
119	CPU8086_internal_DIV(val,divisor,quotient,remainder,error,resultbits,SHLcycle,ADDSUBcycle,applycycles,1,quotientnegative,remaindernegative); //Execute the division as an unsigned division!
120	if (*error==0) //No error has occurred? Do post-processing of the results!
121	{
122		if (quotientnegative) //The result is negative?
123		{
124			*quotient = (~*quotient)+1; //Apply the new sign to the result!
125		}
126		if (remaindernegative) //The remainder is negative?
127		{
128			*remainder = (~*remainder)+1; //Apply the new sign to the remainder!
129		}
130	}
131}

1//Universal DIV instruction for x86 DIV instructions!
2/*
3
4Parameters:
5	val: The value to divide
6	divisor: The value to divide by
7	quotient: Quotient result container
8	remainder: Remainder result container
9	error: 1 on error(DIV0), 0 when valid.
10	resultbits: The amount of bits the result contains(16 or 8 on 8086) of quotient and remainder.
11	SHLcycle: The amount of cycles for each SHL.
12	ADDSUBcycle: The amount of cycles for ADD&SUB instruction to execute.
13	issigned: Signed division?
14	quotientnegative: Quotient is signed negative result?
15	remaindernegative: Remainder is signed negative result?
16
17*/
18void CPU80386_internal_DIV(uint_64 val, uint_32 divisor, uint_32 *quotient, uint_32 *remainder, byte *error, byte resultbits, byte SHLcycle, byte ADDSUBcycle, byte *applycycles, byte issigned, byte quotientnegative, byte remaindernegative)
19{
20	uint_64 temp, temp2, currentquotient; //Remaining value and current divisor!
21	uint_64 resultquotient;
22	byte shift; //The shift to apply! No match on 0 shift is done!
23	temp = val; //Load the value to divide!
24	*applycycles = 1; //Default: apply the cycles normally!
25	if (divisor==0) //Not able to divide?
26	{
27		*quotient = 0;
28		*remainder = temp; //Unable to comply!
29		*error = 1; //Divide by 0 error!
30		return; //Abort: division by 0!
31	}
32
33	if (CPU_apply286cycles()) /* No 80286+ cycles instead? */
34	{
35		SHLcycle = ADDSUBcycle = 0; //Don't apply the cycle counts for this instruction!
36		*applycycles = 0; //Don't apply the cycles anymore!
37	}
38
39	temp = val; //Load the remainder to use!
40	resultquotient = 0; //Default: we have nothing after division! 
41	nextstep:
42	//First step: calculate shift so that (divisor<<shift)<=remainder and ((divisor<<(shift+1))>remainder)
43	temp2 = divisor; //Load the default divisor for x1!
44	if (temp2>temp) //Not enough to divide? We're done!
45	{
46		goto gotresult; //We've gotten a result!
47	}
48	currentquotient = 1; //We're starting with x1 factor!
49	for (shift=0;shift<(resultbits+1);++shift) //Check for the biggest factor to apply(we're going from bit 0 to maxbit)!
50	{
51		if ((temp2<=temp) && ((temp2<<1)>temp)) //Found our value to divide?
52		{
53			CPU[activeCPU].cycles_OP += SHLcycle; //We're taking 1 more SHL cycle for this!
54			break; //We've found our shift!
55		}
56		temp2 <<= 1; //Shift to the next position!
57		currentquotient <<= 1; //Shift to the next result!
58		CPU[activeCPU].cycles_OP += SHLcycle; //We're taking 1 SHL cycle for this! Assuming parallel shifting!
59	}
60	if (shift==(resultbits+1)) //We've overflown? We're too large to divide!

61	{
62		*error = 1; //Raise divide by 0 error due to overflow!
63		return; //Abort!
64	}
65	//Second step: substract divisor<<n from remainder and increase result with 1<<n.
66	temp -= temp2; //Substract divisor<<n from remainder!
67	resultquotient += currentquotient; //Increase result(divided value) with the found power of 2 (1<<n).
68	CPU[activeCPU].cycles_OP += ADDSUBcycle; //We're taking 1 substract and 1 addition cycle for this(ADD/SUB register take 3 cycles)!
69	goto nextstep; //Start the next step!
70	//Finished when remainder<divisor or remainder==0.
71	gotresult: //We've gotten a result!
72	if (temp>((1ULL<<resultbits)-1)) //Modulo overflow?
73	{
74		*error = 1; //Raise divide by 0 error due to overflow!
75		return; //Abort!		
76	}
77	if (resultquotient>((1ULL<<resultbits)-1ULL)) //Quotient overflow?
78	{
79		*error = 1; //Raise divide by 0 error due to overflow!
80		return; //Abort!		
81	}
82	if (issigned) //Check for signed overflow as well?
83	{
84		/*
85		if (checkSignedOverflow(temp,64,resultbits,remaindernegative))
86		{
87			*error = 1; //Raise divide by 0 error due to overflow!
88			return; //Abort!
89		}
90		*/
91		if (checkSignedOverflow(resultquotient,64,resultbits,quotientnegative))
92		{
93			*error = 1; //Raise divide by 0 error due to overflow!
94			return; //Abort!
95		}
96	}
97	*quotient = resultquotient; //Quotient calculated!
98	*remainder = temp; //Give the modulo! The result is already calculated!
99	*error = 0; //We're having a valid result!
100}
101
102void CPU80386_internal_IDIV(uint_64 val, uint_32 divisor, uint_32 *quotient, uint_32 *remainder, byte *error, byte resultbits, byte SHLcycle, byte ADDSUBcycle, byte *applycycles)
103{
104	byte quotientnegative, remaindernegative; //To toggle the result and apply sign after and before?
105	quotientnegative = remaindernegative = 0; //Default: don't toggle the result not remainder!
106	if (((val>>63)!=(divisor>>31))) //Are we to change signs on the result? The result is negative instead! (We're a +/- or -/+ division)
107	{
108		quotientnegative = 1; //We're to toggle the result sign if not zero!
109	}
110	if (val&0x8000000000000000ULL) //Negative value to divide?
111	{
112		val = ((~val)+1); //Convert the negative value to be positive!
113		remaindernegative = 1; //We're to toggle the remainder is any, because the value to divide is negative!
114	}
115	if (divisor&0x80000000) //Negative divisor? Convert to a positive divisor!
116	{
117		divisor = ((~divisor)+1); //Convert the divisor to be positive!
118	}
119	CPU80386_internal_DIV(val,divisor,quotient,remainder,error,resultbits,SHLcycle,ADDSUBcycle,applycycles,1,quotientnegative,remaindernegative); //Execute the division as an unsigned division!
120	if (*error==0) //No error has occurred? Do post-processing of the results!
121	{
122		if (quotientnegative) //The result is negative?
123		{
124			*quotient = (~*quotient)+1; //Apply the new sign to the result!
125		}
126		if (remaindernegative) //The remainder is negative?
127		{
128			*remainder = (~*remainder)+1; //Apply the new sign to the remainder!
129		}
130	}
131}

1SAL1=OK
2SALi=OK
3SALr=Flags problems
4SAR1=OK
5SARi=OK
6SARr=OK
7SHR1=OK
8SHRi=OK
9SHRr=Flags problems
10ROL1=OK
11ROLi=Flags problems(overflow flag not set?)
12ROLr=Carry flag problems
13ROR1=OK
14RORi=OK
15RORr(b/w)=Carry flag problems
16RORr(d)=OK
17RCL1=OK
18RCLi=Overflow flag problems(not set) at word variant only.
19RCLr=OK
20RCR1=OK
21RCRi=Overflow flag problems(not set).
22RCRr=Carry flag problems(set/not set).

1byte op_grp2_8(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER word s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt;
5	//word backup;
6	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
7	numcnt = cnt; //Save count!
8	s = oper1b;
9	switch (thereg) {
10	case 0: //ROL r/m8
11		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
12		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
13		for (shift = 1; shift <= numcnt; shift++) {
14			tempCF = ((s&0x80)>>7); //Save MSB!
15			s = (s << 1)|tempCF;
16		}
17		FLAGW_CF(s&1); //Set carry flag!
18		if (cnt==1) FLAGW_OF(((s >> 7) & 1)^FLAG_CF);
19		break;
20
21	case 1: //ROR r/m8
22		if (EMULATED_CPU>=CPU_80386) numcnt &= 7; //Operand size wrap!
23		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
24		for (shift = 1; shift <= numcnt; shift++) {
25			tempCF = (s&1); //Save LSB!
26			s = (s >> 1) | (tempCF << 7);
27			FLAGW_CF(tempCF); //Set carry flag!
28		}
29		if (cnt==1) FLAGW_OF((s >> 7) ^ ((s >> 6) & 1));
30		break;
31
32	case 2: //RCL r/m8
33		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
34		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
35		for (shift = 1; shift <= numcnt; shift++) {
36			tempCF = ((s&0x80)>>7); //Save MSB!
37			s = (s << 1)|FLAG_CF; //Shift and set CF!
38			FLAGW_CF(tempCF); //Set CF!
39		}
40		if (cnt==1) FLAGW_OF(((s >> 7) & 1)^FLAG_CF); //OF=MSB^CF
41		break;
42
43	case 3: //RCR r/m8
44		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
45		if (EMULATED_CPU>=CPU_80386) numcnt %= 9; //Operand size wrap!
46		if (cnt==1) FLAGW_OF((s >> 7) ^ FLAG_CF);
47		for (shift = 1; shift <= numcnt; shift++) {
48			tempCF = (s&1); //Save LSB!
49			s = (s >> 1) | (FLAG_CF << 7);
50			FLAGW_CF(tempCF);
51		}
52		break;
53
54	case 4: case 6: //SHL r/m8
55		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
56		//FLAGW_AF(0);
57		for (shift = 1; shift <= numcnt; shift++) {
58			if (s & 0x80) FLAGW_CF(1); else FLAGW_CF(0);
59			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
60			s = (s << 1) & 0xFF;

61		}
62		if (numcnt==1) { if (FLAG_CF==(s>>7)) FLAGW_OF(0); else FLAGW_OF(1); }
63		flag_szp8((uint8_t)(s&0xFF)); break;
64
65	case 5: //SHR r/m8
66		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
67		if (numcnt==1) { if (s&0x80) FLAGW_OF(1); else FLAGW_OF(0); }
68		//FLAGW_AF(0);
69		for (shift = 1; shift <= numcnt; shift++) {
70			FLAGW_CF(s & 1);
71			//backup = s; //Save backup!
72			s = s >> 1;
73			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
74		}
75		flag_szp8((uint8_t)(s & 0xFF)); break;
76
77	case 7: //SAR r/m8
78		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
79		msb = s & 0x80;
80		//FLAGW_AF(0);
81		for (shift = 1; shift <= numcnt; shift++) {
82			FLAGW_CF(s & 1);
83			//backup = s; //Save backup!
84			s = (s >> 1) | msb;
85			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
86		}
87		byte tempSF;
88		tempSF = FLAG_SF; //Save the SF!
89		/*flag_szp8((uint8_t)(s & 0xFF));*/
90		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
91		if (!numcnt) //Nothing done?
92		{
93			FLAGW_SF(tempSF); //We don't update when nothing's done!
94		}
95		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
96		{
97			flag_szp8(s); //Affect sign as well!
98			FLAGW_OF(0); //Cleared!
99		}
100		else if (numcnt) //Anything shifted at all?
101		{
102			flag_szp8(s); //Affect sign as well!
103			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
104			{
105				FLAGW_OF(0); //Cleared with count as well?
106			}
107		}
108		break;
109	}
110	op_grp2_cycles(numcnt, varshift);
111	return(s & 0xFF);
112}
113
114word op_grp2_16(byte cnt, byte varshift) {
115	//word d,
116	INLINEREGISTER uint_32 s, shift, tempCF, msb;
117	INLINEREGISTER byte numcnt;
118	//word backup;
119	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
120	numcnt = cnt; //Save count!
121	s = oper1;
122	switch (thereg) {
123	case 0: //ROL r/m16
124		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
125		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
126		for (shift = 1; shift <= numcnt; shift++) {
127			tempCF = ((s&0x8000)>>15); //Save MSB!
128			s = (s << 1)|tempCF;
129		}
130		FLAGW_CF(s&1); //Set carry flag!
131		if (cnt==1) FLAGW_OF(((s >> 15) & 1)^FLAG_CF);
132		break;
133
134	case 1: //ROR r/m16
135		if (EMULATED_CPU>=CPU_80386) numcnt &= 0xF; //Operand size wrap!
136		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
137		for (shift = 1; shift <= numcnt; shift++) {
138			tempCF = (s&1); //Save LSB!
139			s = (s >> 1) | (tempCF << 15);
140			FLAGW_CF(tempCF); //Set carry flag!
141		}
142		if (cnt==1) FLAGW_OF((s >> 15) ^ ((s >> 14) & 1));
143		break;
144
145	case 2: //RCL r/m16
146		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
147		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
148		for (shift = 1; shift <= numcnt; shift++) {
149			tempCF = ((s&0x8000)>>15); //Save MSB!
150			s = (s << 1)|FLAG_CF; //Shift and set CF!
151			FLAGW_CF(tempCF); //Set CF!
152		}
153		if (cnt==1) FLAGW_OF(((s >> 15) & 1)^FLAG_CF); //OF=MSB^CF
154		break;
155
156	case 3: //RCR r/m16
157		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
158		if (EMULATED_CPU>=CPU_80386) numcnt %= 17; //Operand size wrap!
159		if (cnt==1) FLAGW_OF((s >> 15) ^ FLAG_CF);
160		for (shift = 1; shift <= numcnt; shift++) {
161			tempCF = (s&1); //Save LSB!
162			s = (s >> 1) | (FLAG_CF << 15);
163			FLAGW_CF(tempCF);
164		}
165		break;
166
167	case 4: case 6: //SHL r/m16
168		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
169		//FLAGW_AF(0);
170		for (shift = 1; shift <= numcnt; shift++) {
171			if (s & 0x8000) FLAGW_CF(1); else FLAGW_CF(0);
172			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
173			s = (s << 1) & 0xFFFF;
174		}
175		if (numcnt==1) { if (FLAG_CF==(s>>15)) FLAGW_OF(0); else FLAGW_OF(1); }
176		flag_szp16((uint16_t)(s&0xFFFF)); break;
177
178	case 5: //SHR r/m16
179		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
180		if (numcnt==1) { if (s&0x8000) FLAGW_OF(1); else FLAGW_OF(0); }
181		//FLAGW_AF(0);
182		for (shift = 1; shift <= numcnt; shift++) {
183			FLAGW_CF(s & 1);
184			//backup = s; //Save backup!
185			s = s >> 1;
186			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
187		}
188		flag_szp16((uint16_t)(s & 0xFFFF)); break;
189
190	case 7: //SAR r/m16
191		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
192		msb = s & 0x8000;
193		//FLAGW_AF(0);
194		for (shift = 1; shift <= numcnt; shift++) {
195			FLAGW_CF(s & 1);
196			//backup = s; //Save backup!
197			s = (s >> 1) | msb;
198			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
199		}
200		byte tempSF;
201		tempSF = FLAG_SF; //Save the SF!
202		/*flag_szp8((uint8_t)(s & 0xFF));*/
203		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
204		if (!numcnt) //Nothing done?
205		{
206			FLAGW_SF(tempSF); //We don't update when nothing's done!
207		}
208		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
209		{
210			flag_szp16(s); //Affect sign as well!
211			FLAGW_OF(0); //Cleared!
212		}
213		else if (numcnt) //Anything shifted at all?
214		{
215			flag_szp16(s); //Affect sign as well!
216			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
217			{
218				FLAGW_OF(0); //Cleared with count as well?
219			}
220		}
221		break;
222	}
223	op_grp2_cycles(numcnt, varshift);
224	return(s & 0xFFFF);
225}

1uint_32 op_grp2_32(byte cnt, byte varshift) {
2	//word d,
3	INLINEREGISTER uint_64 s, shift, tempCF, msb;
4	INLINEREGISTER byte numcnt;
5	//word backup;
6	//if (cnt>0x8) return(oper1b); //NEC V20/V30+ limits shift count
7	numcnt = cnt; //Save count!
8	s = oper1d;
9	switch (thereg) {
10	case 0: //ROL r/m32
11		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
12		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
13		for (shift = 1; shift <= numcnt; shift++) {
14			tempCF = ((s&0x80000000)>>31); //Save MSB!
15			s = (s << 1)|tempCF;
16		}
17		FLAGW_CF(s&1); //Set carry flag!
18		if (cnt==1) FLAGW_OF(((s >> 31) & 1)^FLAG_CF);
19		break;
20
21	case 1: //ROR r/m32
22		if (EMULATED_CPU>=CPU_80386) numcnt &= 0x1F; //Operand size wrap!
23		else if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
24		for (shift = 1; shift <= numcnt; shift++) {
25			tempCF = (s&1); //Save LSB!
26			s = (s >> 1) | (tempCF << 31);
27			FLAGW_CF(tempCF); //Set carry flag!
28		}
29		if (cnt==1) FLAGW_OF((s >> 31) ^ ((s >> 30) & 1));
30		break;
31
32	case 2: //RCL r/m32
33		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
34		for (shift = 1; shift <= numcnt; shift++) {
35			tempCF = ((s&0x80000000)>>31); //Save MSB!
36			s = (s << 1)|FLAG_CF; //Shift and set CF!
37			FLAGW_CF(tempCF); //Set CF!
38		}
39		if (cnt==1) FLAGW_OF(((s >> 31) & 1)^FLAG_CF); //OF=MSB^CF
40		break;
41
42	case 3: //RCR r/m32
43		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
44		if (cnt==1) FLAGW_OF((s >> 31) ^ FLAG_CF);
45		for (shift = 1; shift <= numcnt; shift++) {
46			tempCF = (s&1); //Save LSB!
47			s = (s >> 1) | (FLAG_CF << 31);
48			FLAGW_CF(tempCF);
49		}
50		break;
51
52	case 4: case 6: //SHL r/m32
53		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
54		//FLAGW_AF(0);
55		for (shift = 1; shift <= numcnt; shift++) {
56			if (s & 0x80000000) FLAGW_CF(1); else FLAGW_CF(0);
57			//if (s & 0x8) FLAGW_AF(1); //Auxiliary carry?
58			s = (s << 1) & 0xFFFFFFFF;
59		}
60		if (numcnt==1) { if (FLAG_CF==(s>>31)) FLAGW_OF(0); else FLAGW_OF(1); }

61		flag_szp32((uint32_t)(s&0xFFFFFFFF)); break;
62
63	case 5: //SHR r/m32
64		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
65		if (numcnt==1) { if (s&0x80000000) FLAGW_OF(1); else FLAGW_OF(0); }
66		//FLAGW_AF(0);
67		for (shift = 1; shift <= numcnt; shift++) {
68			FLAGW_CF(s & 1);
69			//backup = s; //Save backup!
70			s = s >> 1;
71			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
72		}
73		flag_szp32((uint32_t)(s & 0xFFFFFFFF)); break;
74
75	case 7: //SAR r/m32
76		if (EMULATED_CPU >= CPU_NECV30) numcnt &= 0x1F; //Clear the upper 3 bits to become a NEC V20/V30+!
77		msb = s & 0x80000000;
78		//FLAGW_AF(0);
79		for (shift = 1; shift <= numcnt; shift++) {
80			FLAGW_CF(s & 1);
81			//backup = s; //Save backup!
82			s = (s >> 1) | msb;
83			//if (((backup^s)&0x10)) FLAGW_AF(1); //Auxiliary carry?
84		}
85		byte tempSF;
86		tempSF = FLAG_SF; //Save the SF!
87		/*flag_szp8((uint8_t)(s & 0xFF));*/
88		//http://www.electronics.dit.ie/staff/tscarff/8086_instruction_set/8086_instruction_set.html#SAR says only C and O flags!
89		if (!numcnt) //Nothing done?
90		{
91			FLAGW_SF(tempSF); //We don't update when nothing's done!
92		}
93		else if (numcnt==1) //Overflow is cleared on all 1-bit shifts!
94		{
95			flag_szp32(s); //Affect sign as well!
96			FLAGW_OF(0); //Cleared!
97		}
98		else if (numcnt) //Anything shifted at all?
99		{
100			flag_szp32(s); //Affect sign as well!
101			if (EMULATED_CPU<=CPU_NECV30) //Valid to update OF?
102			{
103				FLAGW_OF(0); //Cleared with count as well?
104			}
105		}
106		break;
107	}
108	op_grp2_cycles32(numcnt, varshift);
109	return(s & 0xFFFFFFFF);
110}