The Rise mP6 pipeline also supports some OOE features which became main stream in sixth generation cpus.

To reduce pipeline stalls and to improve data movement efficiency, the Rise™mP6™ processor resolves data dependency […]
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To reduce pipeline stalls and to improve data movement efficiency, the Rise™mP6™ processor resolves data dependency conflicts with the following features:
• Register Re–mapping
• Operand Forwarding
• Result Forwarding
• Zero Cycle Data Bypass
• Arithmetic Pairing

http://datasheets.chipdb.org/Rise/Kirin_WEB2.pdf

If the Vortex86SX still uses one of these execution pipelines, there's no way you could describe it as a 486 cpu except in terms of performance.

the mp6 had a lot of things that were cut out to make vortex86sx. if it only supports a 486 instruction set, no fancy execution pipelines or different caching, or anything else make it not a 486 level chip. you cant describe it as anything but a 486 soc chip.

the vortex86sx/dx reduced the pipeline length even further from the vortex86 (which from memory was the same as the mp6).

what are some examples of vortex86(sx) implementations that are COTS?

maxtherabbit wrote on 2020-04-28, 17:12:

what are some examples of vortex86(sx) implementations that are COTS?

Mostly industrial stuff, usually PC/104.
https://www.wdlsystems.com/embedded/sbc/custi … stomerprice:asc

BloodyCactus wrote on 2020-04-28, 16:30:

the mp6 had a lot of things that were cut out to make vortex86sx. if it only supports a 486 instruction set, no fancy execution pipelines or different caching, or anything else make it not a 486 level chip. you cant describe it as anything but a 486 soc chip.

the vortex86sx/dx reduced the pipeline length even further from the vortex86 (which from memory was the same as the mp6).

Well, let me ask, would a P54 CPU design with the V pipeline hacked off be a 486?

Yes, the Vortex86 SX is described as six stage instead of eight for the mP6. More specifically, the mP6 has a two stage fetch (three when the buffer isn't empty) in front of a six stage integer pipeline.

Maybe the SX pipeline has been shortened. Maybe they're just quoting the length of the integer pipeline. Tellingly, the SX appears to support CMPXCHG8B (according to the ReactOS folks) which is definitely not part of the 486 instruction set. Thus at least the instruction decoder logic has been altered if the starting point was a 486. CMPXCHG8B was introduced with the P5 design.

gdjacobs wrote on 2020-04-28, 18:32:

Well, let me ask, would a P54 CPU design with the V pipeline hacked off be a 486?

no... because it would still be 100% pentium instruction compatible. we had celerons with no cache, and celerons with cache.. instruction wise they were 100% compat.
its not about the cache, its about the instruction set. why is that so hard for you to grasp?

gdjacobs wrote on 2020-04-28, 18:32:

Yes, the Vortex86 SX is described as six stage instead of eight for the mP6. More specifically, the mP6 has a two stage fetch (three when the buffer isn't empty) in front of a six stage integer pipeline.

Maybe the SX pipeline has been shortened. Maybe they're just quoting the length of the integer pipeline. Tellingly, the SX appears to support CMPXCHG8B (according to the ReactOS folks) which is definitely not part of the 486 instruction set. Thus at least the instruction decoder logic has been altered if the starting point was a 486. CMPXCHG8B was introduced with the P5 design.

they also say it supports MMX, which is false.

Keep in mind that Vortex86SX cannot run WinXP because it lacks CMPXCHG8B istruction

Apparently the MX + DX versions has CMPXCHG8B with its FPU.