supercordo wrote on 2024-02-29, 01:17:

Nice Work!!! How much for one?

We have to get the revision taken care of first.
I have no plans to produce these, but might have 2 modules/kits available in the end (and possibly couple of bare pcb's)

majestyk wrote on 2024-02-28, 21:25:

This should be easy to fix in layout "Rev. 1.1".

rev 2.3 now :]
DOC13630 has copper 2.0 designator in lower right corner.
Yours has 2.1.
Funny prototype miisalo managed to fix for RockstarRunner was 2.2. Height when inserted 28.2mm, height including slot 35.6mm.
Github updated. For 2.3 I decide to bite the bullet and shrink it as much as possible without being painful to reroute, it should be almost the height of original. I also made tracks and silkscreen text slightly thicker and worked on clearances. Height when inserted 26.3mm, height including slot 33.6mm. Bigger cap footprint is still too big.

Now I need confirmation size selection works as described, someone with whole Globalyst computer measuring if it fits with floppy on top, and absolute premium would be majestyk testing FIC 486-PAK-3 for compatibility.

What I can say about current proto I have now:
With some sanding, it will insert ok, but fit is tight.
Divider is ok, marks on fingers indicate good alignment, do not recommend shrinking the gap.
miisalo was managing to solder the rams ok, particularly after doing couple of chips, but observed that making the pads bit bigger would ease the job.
Globalyst 510 has floppy on opposite side of case, clearance is not an issue with this machine.

RockstarRunner wrote on 2024-02-29, 09:54:

miisalo was managing to solder the rams ok, particularly after doing couple of chips, but observed that making the pads bit bigger would ease the job.

Yeah, pads need to go more under the chips as curved pins are not even touching the pads and I had to bridge them with solder. I have really good stereo microscope up to 40x so it wasn't so hard but still had to inspect every chip and fix few connections afterwards. With bigger pads, using paste would work too.

Btw, those ceramics just needed bit of creative soldering to connect the pads made for tantalums 😁

Excellent work, I love project like this. Will you make it open source?

Paar wrote on 2024-02-29, 15:10:

Will you make it open source?

ItAlwaysHasBeen_meme.gif 😉

miisalo wrote on 2024-02-29, 11:02:

Yeah, pads need to go more under the chips as curved pins are not even touching the pads and I had to bridge them with solder. I have really good stereo microscope up to 40x so it wasn't so hard but still had to inspect every chip and fix few connections afterwards. With bigger pads, using paste would work too.

So the footprint is too wide despite being the dedicated one downloaded from digikey https://www.digikey.fi/en/models/1555403 for this very chip 😐 7.6mm inner distance while 61C256AL datasheet demands 6.2-7.3. Its almost like this chip is made for SOIC-28 footprint.

Prototype Test Results

| Benchmark | No L2 Cache | 256K L2 Cache | Percentage change |
----------------------------------------------------
| 3DBench Slow | 52.6 | 66.6 | +26% |
| 3DBench Fast | 50.0 | 62.9 | +26% |
| Chris's 3DB | 34.2 fps | 38.3 fps | +12% |
| Chris's 3DB VGA | 10.3 fps | 11.5 fps | +12% |
| PC Player | 14.1 | 15.8 | + 12% |
| PC Player VGA | 5.3 | 5.5 | +4% |
| Doom Max | 29.8 fps | 35.9 fps | 20% |
| Quake TD | 9.5 fps | 10.3 fps | +8% |
| TopBench | 218 | 256 | 18% |
| SysInfo CPU | 128.0 | 198.1 | +55% |

Memory speed measurements
------------------------
| Cache Check |
No Cache ....| L1: 101, Main: 30.1
256K Cache | L1: 102.7, L2: 42.9, Main: 21.1

| SpeedSys |
No Cache ....| Mem Band: 76.15, CPU: 39.27, L1: 58.55, Main: 29.55
256K Cache | Mem Band: 47.37, CPU: 42.67, L1: 66.4, L2: 37,5, Main: 23.9

All in all, some pretty appreciable improvements, such as 20% improvement in Doom, nice!
Importantly, the external cache mode should be set to Write Back, such as this module supports, otherwise improvements are marginal if set to Write Through.

I seem to have taken a hit to system memory bandwidth after adding the cache, maybe some bios settings need tweaking.
Cache Check reports 19 clocks, up from 13.3 clocks without cache
@majestyk can you send me your bios settings for your GAC-2 ?
I will update these results, if I find a solution for this.
I did manage to make it a bit better, see post below

RockstarRunner wrote on 2024-02-29, 16:58:

I seem to have taken a hit to system memory bandwidth after adding the cache, maybe some bios settings need tweaking.

I'm not sure if it's possible to tweak it, I think I've read somewhere it's a quirk of the VIA chipset when using L2 cache. But maybe you'll come with something surprising 😉.

Setting cache timing to Turbo improved things a bit (previous tests were set to Fast)

SpeedSys
Memory bandwidth: 55.04
System score: 42.67
L1: 66.6
L2: 43.89
Main: 24.93

Doom max: 37.2 fps
Quake TD: 10.6 fps

This gets me right about Majestyk's scores posted on page 1

I'm going to run ctcm when I get the chance, to see if the tag is behaving, as that seems to be a typical reason regarding wb cache and nerfed memory bandwidth.

Yep, that's not the issue, oh well, it's another confirmation the cache module is working.

Chip on 2.4 paper version

Have you considered using a DX4 WB or 5x86 CPU?

Briefly, but I have faster machines if I need even more speed. Besides those 5x86 CPUs are just collector prices these days

Nice work!

Main memory speed hit is often to be expected when introducing cache in front of it - the extra latency of reading / writing through the cache (even though it's substantially faster than memory) will impact things. I wouldn't worry about it - the overall speed up of having the next memory location in the cache more often than not will more than make up for it... as your benchmarks indicate!

Really good to see open source solutions for proprietary parts like this!

RockstarRunner wrote on 2024-03-01, 18:36:

Chip on 2.4 paper version
IMG_20240301_203533.jpg

Looks like legs finally land in middle of pads and its perfect for hotplate/hotair/oven soldering, but will still be a PITA to someone with only soldering iron. Slowly getting there, Ill make pads slightly longer 😀 There is ample space. Now that I got familiar with the design I could probably cram it all in at half the width of original module 😜 Ill also move few caps around, CB1 CB2 and CB3 are so close to each other two of them dont contribute anything.

Maybe last try:
bigger pads on sram footprint, should be hand solderable now
height 26.3mm -> 25.9mm
small caps redistributed, one big cap removed

Results of 64/128KB configurations

Sorry this has taken so long.
This is what happens when I configure the jumpers to 64 and 128, with the full set of srams installed (just like 256k mode).

64

64kb is recognized, but the system just sits there before actually running config.sys

128

System just sits there after performing memory count.

Is the problem that you would need to install the correct SRAM configuration according to jumpers, or does the selection simply not work?

The populated chips must match the jumpering, just like when the chips, buffers and jumpers are on the mainboard.
Basically there´s no reason to use less than 256K, the TAG address lines are 7+1 for dirty TAG so we have only half of the cacheable area available.

Im pretty sure I got half the cache working on wrongly jumpered board once. Will have to look at the diagram and ponder this some more.

I still vote for just removing the jumpers all together, and hard wire it for 256k 😁