I think this is a pic of a non plus sharptooth.

🤔

Need pic pf 2+ and 3+ though.

Found these images, no indication of what the chips are but it’s clear that heat is needed to remove the chip without destroying it

I can provide a photo of a delidded K6-2+, but not a K6-3+.

I've taken the IHS off of several K6-2+ CPUs over the years, but the actual increase in clock speed I achieved by doing so has been pretty minimal. Perhaps I've been lucky, but by using a single edged razor on all four corners the shield has come right off with no damage to the core.

When they were less than 5 years old, the non-plus K6-2 had a "wet" thermal paste on the die, the corners were more like hard grey silicone or slightly rubbery epoxy or something, that you could rock a razorblade around to eventually slice through. However, the dies were still on the crunchy side, and I've seen pics of durons, thunderbirds, coppermines have their dies get ripped up from thermal paste stiction and rough HSF removal, so not sure what to make of the pics here. Don't know whether they are worst case hamfisted spreader removals (not a fan of the clamp it in a vice method) or extremely careful ones by ppl who knew what they were doing that failed anyway.

Repo Man11 wrote on 2021-12-09, 13:56:

I've taken the IHS off of several K6-2+ CPUs over the years, but the actual increase in clock speed I achieved by doing so has been pretty minimal.

Yah that's what I've found in general on prior K6 class, doesn't get you higher POST speeds, may stabilise marginal overclocks. Probably worth about "half" a speed grade, ~25Mhz. So if highest stable is say 475 and you can POST 500 but it's crashy, then maybe spreader delete and decent sink give you 500 stable.

This is a decapped K6-2E+ 570.

Repo Man11 wrote on 2021-12-10, 03:29:

This is a decapped K6-2E+ 570.

Sweet! Can we get a high res of the middle all cleaned up showing all the tiny gold pads?

Eventually hopefully someone shows up with a 2+ and a 3+ and can do some continuity measurements I’m wondering if amd didn’t pop a fuse in the package in order to kill the 128k of cache. Maybe it can be re bridged

I have both K6-2+ and K6-III+ CPUs but not sure I want to decap any of them.

Do we really think that the K6-2+ and K6-III+ were the same die?

Maybe I will as they are really easy to decap unless they are wildly different than decapping regular K6-2 CPUs.

cyclone3d wrote on 2021-12-10, 05:35:

I have both K6-2+ and K6-III+ CPUs but not sure I want to decap any of them.

Do we really think that the K6-2+ and K6-III+ were the same die?

Maybe I will as they are really easy to decap unless they are wildly different than decapping regular K6-2 CPUs.

We got a pic of the 2+ so let’s see a 3+ and go from there.

If you have a caliper and can measure the die that would help

Here is a regular K6-III
https://www.alamy.com/amd-k6-iii-sharptoothmo … e231882207.html

I might help. I think I have one dead K6-3+ 400ATZ. Will check tonight...

kixs wrote on 2021-12-10, 09:36:

I might help. I think I have one dead K6-3+ 400ATZ. Will check tonight...

what did you find?

Repo Man11 wrote on 2021-12-10, 03:29:

This is a decapped K6-2E+ 570.

do you see any places on that that may make sense to get measurements from?

like places they may have used current to blow links to sever the cache?

I'm hoping that when in the factory before the heat spreader that they all basically were the same until amd did something

As it happens I didn't get to it yet. But I'm also not sure if you still need it?

kixs wrote on 2022-01-20, 07:16:

As it happens I didn't get to it yet. But I'm also not sure if you still need it?

yes we haven't found anyone with a de lidded 3+ yet

may call on you for some measurements also

need one or two people with a 2+ and a 3+ and ability to upload high res pic and take measurments

we are hoping to figure out how the cache was disabled and turn 2+ into 3+

I would help but I don't want to de lid any of mine (yet)

Intel was selling Pentium CPUs that had defect(s) in their on-chip L2 caches as Celerons by deactivating the half with a defect.
What if AMD did the same with their III+ / 2+ CPUs? "Reactivating" the missing half would result in a CPU with unusable L2 cache.

majestyk wrote on 2022-01-20, 07:40:

Intel was selling Pentium CPUs that had defect(s) in their on-chip L2 caches as Celerons by deactivating the half with a defect.
What if AMD did the same with their III+ / 2+ CPUs? "Reactivating" the missing half would result in a CPU with unusable L2 cache.

Enable it, find out, disable if no go. 😀

Chances are that AMD followed a price discrimination policy and sold faultless "castrated" III+ chips as 2+ to meet the demand for cheaper mobile CPUs.

I´m not sure if I remember this correctly but didn´t a larger cache (in the same CPU) mean a lower maximum CPU speed?

majestyk wrote on 2022-01-20, 07:57:

Chances are that AMD followed a price discrimination policy and sold faultless "castrated" III+ chips as 2+ to meet the demand for cheaper mobile CPUs.

I´m not sure if I remember this correctly but didn´t a larger cache (in the same CPU) mean a lower maximum CPU speed?

Well, since 2+ chips have the mhz records on socket 7 yeah, it seems less cache more clock.

I wonder if these overclockers sometimes disabled cache entirely?

Still haven’t been able to find anyone who owns a k6-3+ that has been de lidded or anyone willing to do it. Anyone? I just can’t bring myself to do it to my 550 🤣