DonutKing wrote on 2022-01-31, 11:54:Hello, sorry to necro an old thread.
I've got a VL/i486SV2 rev 1.7 modded to GX4 using this guide
Specs:
Am5x86-133
16MB single […]
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Hello, sorry to necro an old thread.
I've got a VL/i486SV2 rev 1.7 modded to GX4 using this guide
Specs:
Am5x86-133
16MB single 60ns SIMM
1024kb L2 cache using a 128kx8 for TAG
VLB ET4000w32/p 2MB
VLB Promise EIDE2000 I/O Controller
AWE64 Gold
Gravis Ultrasound Classic
2GB CF card HDD
Sony CDU55E CDROM
I was running the BIOS version linked in this thread but I found that with L1 WB enabled I was getting choppy digital audio, and also some intermittent issues with my floppy drive - I could copy files off it but straight after I would get strange characters in DIR A: output. Presumably there are some DMA issues.
I found that disabling the L1 WB by removing the orange jumpers in the document in the link above fixed my sound issues.
Alternatively, installing a DX4 Overdrive which doesn't support L1 WB mode did not exhibit the issue.
Has anyone had similar issues with a REV1.7 board?
Perhaps BIOS version 0402.001 is not 100% compatible with this version of the board?
Some other questions:
-does anyone know what JP24 does on this board? it is unmarked on my board, and it doesn't seem to match up with any of the manuals I find online. ON my board it is a single jumper near the edge, the manuals usually show it as a group of 3 jumpers for setting the bus speed.
-I find that the BIOS setting 'Local Bus Ready' is somewhat unstable when set to 'Transparent'; I have to set to 'Synchronize' for best stability. Transparent mode gives a small performance boost in benchmarks. Other people have the same experience?
Latest BIOS should work fine (if possible get the version modded to enable dirty tag bit for L2 WB). I think the jumpers for setting L1 WB in that thread are not entirely correct, please follow my guide, those jumpers should be the same on 1.7 and 1.8:
- JP16 pins 1-2 (this connects the WB/WT# pin of the CPU to a pull-up resistor)
- JP17 pins 2-3 (this connects the W/R# output to the INV input of the CPU)
- JP18 pins 2-3 (this connects the HITM# input of the chipset to the HITM# output of the CPU)
- Finally, set both JP5 and JP6 to 1-2 for the proper L1 WB trap setting of the chipset
I also suggest to set the power management jumpers: JP16 3-4 (SRESET) and 5-6 (SMI ACT), as well as JP18 4-5 (SMI)
Also, I've found out that even though I can set the tightest timings with a DX4-100 or AMD 5x86-133, I need to disable the "DRAM Write Burst" option in the BIOS when using L1 WB or there will be instabilities. You may want to check that.
- Regarding JP24, I need to check the manual as I don't remember, will reply again when I have the info
- The "Synchronize" vs "Transparent" seems to depend on the video card in my experience. For example, my S3 Trio64 works fine and gets a small performance increase with "Transparent", while an ET4000/W32P seems to work and gets the performance increase but some games fail to load (for example Rise of the Triad). So it seems to be a trial and error process which requires some extensive testing (not sure if the additional performance is worth it)
PC-Engineer wrote on 2022-01-31, 14:21:The SV2GX4 has its problems with L1WB, but not with all CPUs. For example, in my Rev. 2.1 board, the Am5x86, the AMD DX4 SV8B, the Intel DX2WB and the Intel DX4 run with L1WB without DMA problems. With the Cx5x86 there are partly problems and with the POD the DMA with L1WB is not possible at all. I have already played with all documented registers, but failed. Very sad, because with the POD@100MHz the board is faster than a real Pentium 100 with Neptune chipset.
The POD unfortunately doesn't seem to work properly with versions < 2.0 of this board... I couldn't find any combination where it was stable, even with L1 set to WT.