what about L2 Tag RAM?
how much difference does the L2 give? have you benchmarked anything with L2 turned off?
what CPU? if K6-2+/3 then there wont be any difference

I haven´t seen 2 MB chips in a QFP-128 package so far.
Given VIA´s MVP3 chipset, for 2MB L2 cache you would need a 32-pin TAG RAM (512K), if there are landings for a 28-pin TAG chip on your mainboard and / or only one position for a QFP-128 L2 chip - forget about 2MB.

For 1 MB L2 cache just replace the existing chip and adapt the 0-ohm resistors accordingly.

@rasz_pl
I am currently trying to get a comprehensive (true) performance benchmark of various CPUs. Starting with early Pentium 1 over to Pentium MMX, Cyrix 6x86 / MII, to RiseMp6, WinChip 1 / 2 to AMD Geode and AMD K6-2 and K6-3+

To do that I use a current Linux Kernel together with AntiX / gentoo Linux while the Kernel is optimized for the respective CPU installed. It then runs I/O based, memory, network etc. tests which can be compared with the other CPUs to get a comprehensive overview of the true potential of these CPUs (under optimal enviroment conditions / optimized code and feature usage.

However, this requires a good amount of RAM. 256 MB at the very minimum, better 512 MB to avoid swapping, which would invalidate any I/O based results.

That´s why I try to equip a SS7 mainboard with ideally 2 MB of L2 cache.

I have several boards available, like the already mentioned Shuttle Ti5VG+ to the GA-5AA and the ASUS P5A, Gigabyte GA-5AX to name a few.
Unfortunately most come with only 512KB of L2 cache. (I sold my EP-MVP3G5 too early)

I took some photos of the Ti5VG+ and it seems it has a TAG ram of 512K as well as two QFP128 pads, one on the component side and one on the back, if I am not mistaken, see photo.

TI5VG+ with 512K SRAM and TAG 512K

Rear view with PCB pad for additional SRAM QFP128 ?

This SRAM / TAG is currently on the board

Does anyone know if the rear pad is a "real" pad and if it´s possible to solder two 8Mbit SRAM chips to it to replace the current 4 Mbit one?

Wishful thinking, you should have kept your MVP3-G5 😀

The TAG chip is 256K, 28 pin [32K x 8] - don´t bother about 2MB cache.

_All_ you can do is add a second 512K cache chip on the flip side or maybe replace the existing 512K by a 1M chip. The 2-chip solution is superior because L2 interleave is possible.

The limits for cacheable RAM area are 256 MB (write through) or 128 MB (write back) with this setup. Many MVP3 boards don´t offer WB L2 due to BIOS limitations or they switch between WB / WT automatically depending on RAM size.