VOGONS


First post, by Rav

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Hi there

UCP 2.0 :

The attachment ucp2.zip is no longer available

Screenshots from my MMX

The attachment ucp2_1.png is no longer available
The attachment ucp2_2.png is no longer available

I got my new UCP in a state that in can finally be published.
The new version is compatible with the following PCI chipsets:
- ALi M1521
- ALi M1531
- ALi M1541
- Intel 440BX
- Intel i815

- ALi M1523
- ALi M1533
- ALi M1543
- Intel PIIX4
- Intel ICH2

I do plan to port (refactor/remake) code for ISA chipset support soon. Plus some improvement / modification probably as for the layout as some options are kind of long so I might change the UI so the top half are the settings and the bottom half, the help... Or maybe update the center vertical line so it's dynamic to auto adjust width according to the stuff in the left column. Once I have ISA stuff back, that will allow me to also configure other PCI stuff that are accessed thru normal I/O ports (for example that BuB S3 fixing stuff)

If you have any idea for improvement or request for chipset, please let me know

Utilisation, you won't be lost, if you ever used Award BIOS. Settings are saved in the same folder as the .exe. Once you made configurations, you can put the thing in the autoexec.bat with /autoload switch, to just load the configured settings.

There is a memory test tool in the program, but it's still alpha-ish and ugly. If you want to test new memory timing/speed settings in memtest86+, you can simply boot using something like QEMM, set the settings and press ctrl-alt-del, it will fastboot (instantly load memtest from the flop) without going back to the BIOS, preserving all settings. If you do that, be sure to not have network drivers loaded as they also don't get reseted and they will DMA packets in the RAM, failing the test.

Note that I have only tested on Ali M1531/M1533 (My system). Settings in yellow in the screenshot are what I changed (Gained 1.5fps on Quake yay!)

There way more interesting options in Ali chipsets.. Intel seam to be way more limited..

Here two chip support file :

The attachment piix4.c is no longer available

,

The attachment ali1541.c is no longer available

.
I welcome peoples making some for other chips that are not listed, and I will add them to UCP2.

User loadable files are planned to be supported in a future version (once I have all structures for all the supported way of patching stuff implemented and stabilised).
Here an example of a register setting for a freetext format (digit between 0 and 31)

{
"PCI Latency Timer",
"Controls the amount of time the M1531 can burst data to the PCI Bus.",
0, 0, 0, 0x0C, // Bus, Dev, Func, Reg
0xF800, // Mask: Bits 7-3
11, // Shift: 3 bits
0, // opt_count: 0 (not used)
{ {NULL, 0} }, // opts: Empty/Unused
0, // current_idx: current or default value
0, // default_idx: default value, populated and first launch from the currently configured setting by the BIOS

INPUT_TYPE_FREEFORM, // It's a number input
0, // Min Value
31 // Max Value
}

Bus, Dev, Func will be removed in the future, just set it all to 0,0,0

Here another one for a setting with choices:
{
"Refresh period", "Period to refresh DRAMs. Longer delay = faster operation.",
0, 0, 0, 0x44, 0x0700, 8,
5, { {"1024 Clk", 0},{"2048 Clk", 1},{"4096 Clk", 2},{"8192 Clk", 3},{"16384 Clk", 4} }, 0, 0,
INPUT_TYPE_LIST, 0, 0
},

Note to people wanting to help submitting chip files.
PCI Configuration mode is accessed via 32 bits chunks and x86 is little endian. So here how to properly set the register

Example register 0x44, bit 2-3.
You take the register from the doc, 0x44, and do "mod 4". you endup with "0", so you do as simply as:
Register "0x44", mask "0C" and shift "2"

Example register 0x46, bit 2-3
0x46 mod 4 is equal to 2, so you have to shift all the stuff 2 times 8 bits on the left
You write it as register "0x44" still (You can also write 0x46, my program do chop the two last bits of the register digit.)
Mask would be "0x0C0000"
shift would be "18" (2 + (2 * 😎)

Last edited by Rav on 2026-04-29, 00:05. Edited 2 times in total.

Reply 2 of 8, by Rav

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marxveix wrote on Yesterday, 10:01:

Does it work cheaper Intel 440 chipsets, like 440zx/440lx/440ex?

Support for more chipsets will be added soon.

Code for chipsets are specific and pinned to them by there VID/DID.

Edit : half support is implemented. If you don't have a supported northbridge, but have a supported southbridge, you will see the setting for the southbridge. And vise versa.
If you configure for say the PIIX4, and later update for a new version that support the 440EX, then the configuration you did for the PII4X will be preserved.

Reply 3 of 8, by carlostex

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Oh wow, this is something i really want to try out. My main retro system is a 430TX chipset which uses the Intel PIIX4 southbridge. I'm wondering what options are available to tweak.

Reply 4 of 8, by jheronimus

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Would be cool to have custom chipset register files like in TweakBIOS or wpcredit. This way users will be able to contribute files for various esoteric chipsets.

MR BIOS catalog
Unicore catalog

Reply 5 of 8, by Rav

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jheronimus wrote on Yesterday, 20:28:

Would be cool to have custom chipset register files like in TweakBIOS or wpcredit. This way users will be able to contribute files for various esoteric chipsets.

I do plan to have external files support in the future.
In the form if a binary format that would contain all the needed stuff.

It's not available yet as I'm not done with all the needed stuff (right now it only support registers in the PCI Configuration mode, no I/O registers or other fancy stuff).
Once I have all the stuff supported and all array structure defined and stable for everything, I plan to release a program that convert between text and binary (both directions)

The files will be in a "chips" subdirectory and UCP2 will scan theses to see if they support some of the present PCI devices.

The save format is already made in a way to support user modifications of registers definitions (it will still load and apply even if the definition get updated to add more stuff, and will also work if the order of the entries in the file change. Only saved stuff that is removed from the files don't get loaded/applied.).

Here is a current built-in file. Feel free to create new one and I can integrate it in the current version.

The attachment ali1541.c is no longer available

Reply 6 of 8, by Rav

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jheronimus wrote on Yesterday, 20:28:

Would be cool to have custom chipset register files like in TweakBIOS or wpcredit. This way users will be able to contribute files for various esoteric chipsets.

Here the support file for the PIIX4 :

The attachment piix4.c is no longer available

Northbridge are.. more interesting but...
It have few ISA stuff, and a lot of IDE timing stuff (Backup your stuff before testing that please)

Reply 7 of 8, by jheronimus

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Rav wrote on Yesterday, 21:11:

Here is a current built-in file. Feel free to create new one and I can integrate it in the current version.

The attachment ali1541.c is no longer available

Nice! I'll try to mess with it on the weekend and add SiS 600, that one really benefits from this.

MR BIOS catalog
Unicore catalog

Reply 8 of 8, by Rav

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Note to people wanting to help submitting chip files.
PCI Configuration mode is accessed via 32 bits chunks and x86 is little endian. So here how to properly set the register

Example register 0x44, bit 2-3.
You take the register from the doc, 0x44, and do "mod 4". you endup with "0", so you do as simply as:
Register "0x44", mask "0C" and shift "2"

Example register 0x46, bit 2-3
0x46 mod 4 is equal to 2, so you have to shift all the stuff 2 times 8 bits on the left
You write it as register "0x44" still (You can also write 0x46, my program do chop the two last bits of the register digit.)
Mask would be "0x0C0000"
shift would be "18" ( 2 + (2 * 8 ))