I have a Tseng ET4000/W32 VLB with 1MB in 8x DIP 44256 chips in sockets. On PCB they are marked as BANK0. There are also unpopulated footprints for another 8 DIP chips marked as BANK1. So I was thinking the same if adding the 2nd bank also gains some speed. Not sure if extra DRAM will be find automatically or I will need to change/add some jumper or resistor somewhere...

Hmm. I believe you would need a W32i or W32p to do interleaving. I don't have any Tseng ET4000 cards yet, so I cannot confirm.

Maybe that's the reason why 2nd bank sockets was not populeted. I just soldered them on but I don't have enough fast 44256 DRAMS (only 8 pcs of 70ns and then some 100ns). I could try put 4 chips to bank 0 and 4 to bank 1...

RayeR wrote on 2026-11-04, 02:05:

I could try put 4 chips to bank 0 and 4 to bank 1...

That configuration is not supported, and likely would not help anyway. The ET4000 series of chips is meant to be used with a 32-bit wide memory bus, which needs 8 of those 4-bit chips per bank to get the preferred bus width. They can work in a degraded 16-bit mode for entry-level cards with only 512K of video memory (four of your chips in bank 0), but there is no support for two interleaved 16-bit banks, which would very likely be significantly inferior to a single 32-bit bank.

Just for completeness: There is a VRAM mode on the ET4000 series that no one uses. That mode splits the 32-bit data bus in two 16-bit busses, one for drawing (using the random access port of the VRAM) and the other one for display (using the serial port). I don't expect that mode to be implemented in the W32, but I'm not sure. I have no idea whether there are any theroretical advantages of the 16-bit VRAM configuration over the 32-bit DRAM configuration. There most likely is an advantage at 512KB (16 bit VRAM vs. 16 bit DRAM), though.

Ok, so at least I could get more colours in VESA modes. BTW is there some video BIOS upgrade for VLB card that has implemented VESA VBE? Currently I have to run some Tseng TSR. There are multiple versions and dunno what's the latest/best one. But all ca do only VBE 1.2 not 2.0. Maye even LFB mode not supported by HW?

You probably want to create a separate thread for that to get more eyes on the question and to keep this thread on topic.

Most of the cards I've tested are all pre-VBE 2.0 video BIOS implementation, and VLB started to sunset before those writing the BIOS planned to implement VBE 2.0. There is quite a bit of variance in terms of which cards are supported well via TSRs - native TSRs, univbe, and univbe versions are going to be quite different from card to card.

You were right. My card is exactly this one: https://theretroweb.com/expansioncards/s/his- … 2-non-i-version
with only W32 chip so no interleaving. But the card manufacturer prepared the PCB for W32i and 2MB. I did a bit of RE over PCB and found that CAS# pins of unpopulated DRAMs goes to CAS4-7# of W32i. I can't find pinout of W32, that pins are not NC but has some unknown meaning but not simply possible to expand it to 2MB non-interleaved. I also tried with 100ns chips and it works too, maybe memory controller is smart and flexible to accomodate to slower DRAMs...
So maybe if I would find some suitable donor of W32i I will swap the chip...
BTW even that NI card performance is not bad, Doom timedemo: ET4000/W32 - 41,56 FPS vs S3 Trio64V+(VLB) - 42,93 FPS...

RayeR wrote on 2026-11-09, 03:26:

BTW even that NI card performance is not bad, Doom timedemo: ET4000/W32 - 41,56 FPS vs S3 Trio64V+(VLB) - 42,93 FPS...

I wonder how much Doom will profit from interleaving. Interleaving mainly does one thing: It increases the bandwidth between the memory and the ET4000 chip for burst access.

It's well known that Doom does byte access to video memory only, which cap out at 16.7MB/s at 33MHz VLB clock even at 0WS with 100% bus utilization. 16.7MB/s isn't that hard to achieve, especially if it were linear and the card can merge the byte writes to 32-bit writes. In that case, it would be around 4.2 mega-dword-accesses per second, that is more than 200ns cycle time. I don't think any FIFO-equipped card would be slow enough to be the bottleneck at that rate. But as all the pseudo-3D engines of that time, wall textures are rendered vertically, not horizontally, so Doom does not write linearly, but the writes are 320 bytes apart, so all the writes of a wall texture hit the same bank!. And they are all single byte writes. 16.7 million byte writes per second would require a cycle time of 60ns, which would require something like 40ns RAM if no page mode is employed. So indeed, video memory performance might be a bottleneck if the CPU is fast enough to spam out a byte every two bus clocks and the ET4000 can take bytes at 0WS (I actually don't know off-hand whether 0WS or 1WS is the limit). But interleaving can't relieve that pressure at all.

Where interleaving really shines is scanning out the display to the monitor. At 320x200 with 256 colors at 60 Hz, the average rate is around 4MB/s. The ET4000 will run the memory cycles to fill it's display FIFO in fast page mode, so 4MB/s is a laughably low rate, and even if interleaving reduces the memory pressure reduced by scan-out, the improvement will be miniscule.

If, on the other hand, you go up to something like 800*600 at 64k colors and 72Hz, that would be around 70MB/s required for scan-out, and rates like that really do profit from interleaving. So don't expect Doom to go crazy when you add interleaving, but expect a very noticable boost in GUI drawing perfermance, especially when utilizing the accelerator. Tseng's datasheet claims 70% to 80% bandwidth increase due to interleaving, which may even cause higher performance boost for drawing, because if without interleaving, 50% of the available bandwidth was used for scan-out and 50% for drawing, and interleaving only actually gets you a 50% boost, all those 50% go to the drawing, the performance requirement for display does not increase, and drawing performance might double.

I'd be interested in seeing DOOM benchmark differences on the ET4000/W32i/p, myself.

For the Vision868, the benchmarks from 1MB -> 2MB were:

DOOM: 43.91 -> 44.12
Fastdoom (Mode Y): 59.277 -> 60.723
Fastdoom (320x200 VBR): 58.811 -> 58.811 (same)
Fastdoom (320x200 VBD): 65.231 -> 67.531
Fastdoom (640x400 VBR): 19.864 -> 19.943
Fastdoom (640x400 VBD): 22.469 -> 24.830

While there were some scores that were within margin of error, there were also noticeable improvements when using Fastdoom VBD modes.

This was just a DX4-100 @ 33 MHz FSB, so there is some headroom available with faster processors and FSB speeds.

Is interleaving the same thing as increasing ram bus width? Because many cards, like Cirrus Logic chips, double the ram bus width when you double the ram. Never heard this referred to as interleaving?

I have a Compaq Prolinea with integrated ET4000. I think it has sockets for video memory, I need to go dig it out and see.

kingcake wrote on 2026-11-09, 23:57:

Is interleaving the same thing as increasing ram bus width? Because many cards, like Cirrus Logic chips, double the ram bus width when you double the ram. Never heard this referred to as interleaving?

I have a Compaq Prolinea with integrated ET4000. I think it has sockets for video memory, I need to go dig it out and see.

Interleaving is a cheap, but often quite effective substitute of increasing the bus width. So RAM chips of a certain can deliver a specific number of access cycles per second (the exact rate depends on the type of cycles: FPM page hits can be way faster than "full RAS cycles"), but there is no need to go into these technicalities. To get a higher data rate, you can ask multiple RAM chips at once, each delivering its data on separate data lines. Typical DIP chips on graphics cards provide 4 bits at a time, so use 8 of them to get 32 bits at a time. Obviously, the available data rate scales with the number of chips, but it comes at a cost: You need a dedicated data pin on the graphics chip for each data bit, and you need a dedicated trace on the board for each data bit. If you need raw performance and cost is no hurdle for you, you know where to find performance: Just increate the bus width.

The idea of interleaving is facilitate two banks of memory connected to the same data lines in a clever way. Using multiple banks is not a new idea, for example, even the original Apple II had 3 banks of main working memory. They used multiple banks just to increase the capacity, though. Every cycle just went to one bank, while the other banks idled. The key observation is that while you access one bank, the memory chips limits how often it can send new data to the data lines, but the data lines need not be active all the time, and this is where interleaying kicks in: You read one set of data bits from the first bank (32 bits for the W32/i), and then have the chips on the first bank prepare the next access, while shutting them off the data lines, and telling the second bank to send data instead. After you got the data from the second bank, you tell the second bank to shut up and prepare its next value and then fetch the value already prepared from the first bank again. This uses the data lines more effectively, because they also transfer data from one bank while the other bank prepares the next access.

Interestingly, the concept of interleaving is in heavy use, even today: When RAM manufacturers upgraded from PC-100/PC-133 SD-RAM to DDR200/DDR266 they were still running the same memory cells at the same speed, they were just putting two "banks" (the term "bank" is heavily overloaded, and is defined to mean something else in SDRAM technology, that's why I use scare quotes) into the chip, with the chip interleaving the two "banks", so while every "bank" still only handles 100/133 million reads/writes per second, by alternating between the "banks", the chip can handle 200/266 million reads/writes a second. And with DDR2, in which the speed was upped from 200 to 400 Mega-Transfers per second to 400 to 800 Mega-Transfers per second, they did not suddenly create any faster memory, they just "deepened" the interleaving by using four instead of two memory "banks", each still handling only 100 to 200 Mega-Transfers per second.

mkarcher wrote on Yesterday, 07:50:

kingcake wrote on 2026-11-09, 23:57:

Is interleaving the same thing as increasing ram bus width? Because many cards, like Cirrus Logic chips, double the ram bus width when you double the ram. Never heard this referred to as interleaving?

I have a Compaq Prolinea with integrated ET4000. I think it has sockets for video memory, I need to go dig it out and see.

Interleaving is a cheap, but often quite effective substitute ...

Ok so basically both techniques for increasing bandwidth, but doubling bus width = larger chip package and more complicated (possibly requiring more layers) pcbs. I would assume doubling bus width = better performance than cheaper interleaving? You say it means the same thing as it does on modern desktops, and modern interleaving doesn't double performance. Sometimes it's only like 20% improvement?

Yes, interleaving would be always less effective than doubling the bus width. It depends how often memory chips can outupt the new data and how long they need to prepare next. Transfer. I would say that interleaving helps rather for slow mem.chips where is more waiting for data than fast chips. Btw have a look at my thread about reapir and memory upgrade the GeForce2 MX400 card. I got cheap variant with only 4 chips that crippled the GPU to use only 64b bus width while the GPU is capable use 128b. There was footprints for another 4 mem.chips on the back side. So i digged spare chip, soldered on and profit. As you can see 3Dmark2k goes almost twice points! So scaling the bus helped a lot in this case...

MrKarcher, thanks for detailed explanation and thoughs, your posts are highly valuable. I understand that interleaving rather helps on some burst access in higer resolutions, I was just curious if also doom could benefit and agree that probably not much. BTW doesn't need the interleaving control of OE# pins of both banks separately? On my card it seems all OE# are just grounded... But I would bet the manufacturer prepared the PCB to make W32i variant...

RayeR wrote on Yesterday, 19:09:

Yes, interleaving would be always less effective than doubling the bus width. It depends how often memory chips can outupt the new data and how long they need to prepare next. Transfer. I would say that interleaving helps rather for slow mem.chips where is more waiting for data than fast chips. Btw have a look at my thread about reapir and memory upgrade the GeForce2 MX400 card. I got cheap variant with only 4 chips that crippled the GPU to use only 64b bus width while the GPU is capable use 128b. There was footprints for another 4 mem.chips on the back side. So i digged spare chip, soldered on and profit. As you can see 3Dmark2k goes almost twice points! So scaling the bus helped a lot in this case...

MrKarcher, thanks for detailed explanation and thoughs, your posts are highly valuable. I understand that interleaving rather helps on some burst access in higer resolutions, I was just curious if also doom could benefit and agree that probably not much. BTW doesn't need the interleaving control of OE# pins of both banks separately? On my card it seems all OE# are just grounded... But I would bet the manufacturer prepared the PCB to make W32i variant...

I will check it out. Yes thanks to both always happy to learn something. It's amazing I still learn something new about these old machines every day here on vogons and I've been working on them for decades. Turtles all the way down.

kingcake wrote on Yesterday, 08:20:

I would assume doubling bus width = better performance than cheaper interleaving? You say it means the same thing as it does on modern desktops, and modern interleaving doesn't double performance. Sometimes it's only like 20% improvement?

Tseng's datasheet indicate a performance gain of 70% to 80% by interleaving according to the marketing blurb at the start of the data sheet, and in chapter 6.3.2.1 "Interleave DRAM interface", it just claims 70% by stating: "The DRAM bandwidth is increased by 1.7 times by using memory interleaving". While you might apply word-mongering to argue whether this sentence means a gain of 170% if read literally, it's obviously not what Tseng intended to say. The datasheet does not indicate exactly how they get to that factor, but it seems plausible:

The ET4000 family (W32 or not) uses fast page mode to access video memory, so consecutive accesses inside a single page are fast. Interleaving the two 32-bit banks only helps if 64 consecutive bits are required, but this applies to a double-width bus as well. The 70% improvement factor probably assumes that most memory cycles transfer at least 64 consecutive bits. This is the case for linear memory reading by the CRTC, and I suppose it is also true for CPU video memory writes if the writes are linear. The ET4000 series of graphics chip contain a write queue for CPU writes, and they likely perform merging of consecutive writes to bigger writes - up to 64 bits in interleave mode. Once in page mode, interleaved accesses deliver 32 bit chunks exactly at twice the speed of non-interleaved mode. Nevertheless, when switching to a different page, the time required to switch the page does not go down due to interleaving, so the latency for switching pages stays the same in interleaved mode. Again, this non-doubling of practical bandwidth also occurs when you double memory width. Tseng estimates that a page switch is expected to happen every 8 to 16 memory accesses "for a typical workload supporting a single CRTC and [accelerator] activity". This would explain why the net gain is just 70% instead of 100%.

Interleaved memory is tricky to get working. The datasheet contains quite strict language:

ET4000/W32i datasheet wrote:

When in an interleaved configuration, any DRAM device that shares a data line with another DRAM device should be as identical as possible to ensure complete compatibility in the DRAM data output's source and sink current. The DRAM should be of the same manufacturer, part number, revision level, and speed. DRAMs should have 50ns or better access time. This degree of compatibility is necessary due to the nature of interleaving which causes one DRAM to turn on while the other is turning off during DRAM read cycles. Another consideration is the Taa (access time from CAS) timing ≤ 27ns when the SCLK = 50MHz. [...]

Field upgradability is impractical because of the stringent control necessary to ensure reliable interleave operation. For this reason it is strongly recommended that field upgrades not be considered for interleave designs.

In my oppinion, this is slightly over-cautious, but "better safe than sorry". I wonder why they recommend 50ns access time, because at 50MHz SCLK (the maximum system clock supported by the W32i) the "page mode cycle time" required is just 40ns, and typical 50ns chips have a page mode cycle time of around 12 to 20ns. Probably some other requirements, like the quoted "access time from CAS" is the basis for this recommendation. OTOH, I don't remember seeing 50ns chips on many actual ET4000 cards.

So I do believe the 70% more bandwidth claim is true, yet the increased bandwidth only translates to higher performance if that bandwidth is actually required! There is a graph in the ET4000/W32i datasheet that estimates a non-interleaved bandwidth of 75-82 MB/s at 8 to 16 transfers per page mode cycle at a system clock of 50MHz. With interleaving, that would be 128-140MB/s. Given a display bandwidth requirement of 35MB/s for 800*600 at 72Hz, even without interleaving around 40MB/s remain for the VL bus or the accelerator. Good look pushing 40MB/s through the front-side bus of a 486DX/2 66. In that mode without use of the accelerator, interleaving will have a miniscule effect if at all for typical games, and I wouldn't expect any 486 game to acutally use 800*600. Things change as soon as you use the acceleration engine to write two-color bitmaps over the bus, or display-memory-to-display-memory copy, or if you want 16 bits per pixel.

You likely misunderstood my remark about modern systems: I was not thinking about dual-channel memory, which is actually more like "doubling bus width" than "interleaving", because the channels have different data lines as far as I know. I was talking about interleaving happening inside a single memory chip. Every new generation of DDR memory doubles the bandwidth compared to the previous generation due to more internal interleaving, not due to memory cells actually working faster:

1DDR(1): 100 to 200 megatransfers on two "banks" yielding DDR200 to DDR400
2DDR2: 100 to 266 megatransfers on four "banks" yielding DDR2-400 to DDR2-1066
3DDR3: 100 to 266 megatransfers on eight "banks" yielding DDR3-800 to DDR3-2133
4DDR4: 100 to 200 megatransfers on sixteen "banks" yielding DDR4-1600 to DDR4-3200
5DDR5: 125 to 275 megatransfers on thirty-two "banks" yielding DDR5-4000 to DDR5-8800

The consideration that doubling the transfer rate of DDR SDRAM chips only doubles the bandwidth during a burst, but does usually not improve the latency a lot, so the effective bandwith typically only is improved by around 70% when going from one DDR generation to the next applies here as well. Also, the consideration that more bandwidth only means more performance if the bandwidth is actually required is very relevant. On modern PCs, single-channel RAM is usually good enough to cater the bandwidth requirement of modern CPUs without integrated graphics and not excessively many cores. A significant performance gain due to dual-channel operation and memory overclocking is typically only observed if the integrated GPU competes with the CPU for memory bandwidth.

RayeR wrote on Yesterday, 19:09:

Yes, interleaving would be always less effective than doubling the bus width. It depends how often memory chips can outupt the new data and how long they need to prepare next. Transfer. I would say that interleaving helps rather for slow mem.chips where is more waiting for data than fast chips.

Since we got synchronous RAM, and DDR RAM has interleaving integrated into the memory chips, I don't think external bank interleaving makes any sense anymore.

RayeR wrote on Yesterday, 19:09:

BTW doesn't need the interleaving control of OE# pins of both banks separately? On my card it seems all OE# are just grounded... But I would bet the manufacturer prepared the PCB to make W32i variant...

The ET4000/W32i doesn't use OE# for bank interleaving: For classic asynchronous DRAM, CAS# also works implicitly as output enable, and the ET4000/W32i has four CAS# lines for bank 0 and four CAS# lines for bank 1. In case of interleaving, CAS0-3# are CAS4-7# negated during the FPM "burst".

As far as !OE goes, in basically all DRAM designs I see, it is always grounded. !WE always wins and is the signal that is used to decide if a read or write has to happen, and general timing is done by !CAS as mkarcher said. Some motherboards also interleave memory banks to reduce power spiking.

Tiido wrote on Today, 19:18:

As far as !OE goes, in basically all DRAM designs I see, it is always grounded. !WE always wins and is the signal that is used to decide if a read or write has to happen, and general timing is done by !CAS as mkarcher said. Some motherboards also interleave memory banks to reduce power spiking.

This stopped to be generally true with the advent of EDO RAM. With EDO RAM, deasserting !CAS does not disable the outputs anymore, so to free the bus for another memory bank, you need to do at least one of

1. Deassert !OE (the obvious way)
2. Deassert !RAS (with the side effect of closing the current page)
3. Pulse !WE

As 72-pin SIMMs do not have !OE, and closing the page every time you need to free the bus, most 486/Pentium chipsets use the third way to tell EDO RAMs to release the bus, which prolongs the memory read cycle by one clock on the first generation of chipsets with EDO support. 168-pin EDO DIMMs fixed the issue of missing !OE, but never got mainstream use because they were quickly superseded by 168-pin SDRAM DIMMs.