SetMul v1.21 - Multiplier control for VIA C3, AMD K6 Mobile and Cyrix 5x86
G. Broers 2014-2017 - Free for non-profit use.DESCRIPTIONThe main purpose of this program is to quickly change the multiplier of VIA C3
and AMD K6 Mobile x86 processors in MS-DOS and Windows 9X. It will display the
multiplier and resulting speed. In addition it can enable and disable processor
L1 and L2 cache.
BACKGROUNDMany DOS game and programs have issues with a CPU speed higher then expected,
while other software benefits from increased CPU speed. Having a means to
adjust the processor speed is important for making a system suitable for a
broad range of vintage software.
Originally a classic Pentium processor multiplier was set through jumpers,
without any means to adjust this through software. Around 2000 came a line of
'mobile' processors specifically aimed for laptops, which had a new feature to
preserve battery life when idle:
-Intel called this feature (Enhanced) SpeedStep.
-AMD called this feature PowerNow!
-VIA/Centaur called this feature Longhaul, but later renamed it to PowerSaver.
In all cases it is about temporarily decreasing the processor multiplier by
software. The resulting net processor speed is the Front Side Bus speed times
the selected multiplier. For example: 66 MHz FSB times 5.5 = 366 MHz.
MULTIPLIER OPTIONSThis table shows the available options for each supported processor:
VIA C3 Samuel 1: 3.0x to 8.0x, 11 choices
VIA C3 Samuel 2 step 0: 3.0x to 8.0x, 11 choices
VIA C3 Samuel 2 step 1+: 3.0x to 12.0x, 16 choices
VIA C3 Ezra: 3.0x to 12.0x, 16 choices
VIA C3 Ezra-T: 3.0x to 16.0x, 27 choices
VIA C3 Nehemiah: 4.0x to 16.0x, 25 choices
AMD K6-2+ / K6-III+: 2.0x to 6.0x, 8 choices (2.5x is excluded)
Cyrix 5x86 1.0x to jumpered multiplier (being 2, 3 or 4), 2 choices
A VIA C3 may, or may not work reliably at a total core speed below 250MHz.
BUILD-IN CACHE OPTIONSDisabling L1 Cache makes a processor very slow, at least half the processing
speed is cut. Disabling L2 Cache also slows the net speed, but has far less
impact.
SetMul allows disabling the L1 cache on any x86 processor from the 486 onwards.
SetMul allows disabling the L2 cache on the K6 Mobile and VIA C3. Note that
the C3 Samuel 1 has no L2 cache.
Contrary to many other cache disabling tools it still works when EMM386 or
Windows 9X are loaded.
PARAMETERS/? - default help screen.
[Multiplier] - as a single digit like '5', or '5.0', or halves like '5.5'.
L1D - L1 Cache Disable.
L1E - L1 Cache Enable.
L2D - L2 Cache Disable.
L2E - L2 Cache Enable.
ICD - L1 I-Cache Disable, on VIA C3. (I-Cache is half the total L1)
ICE - L1 I-Cache Enable, on VIA C3. (I-Cache is half the total L1)
BPD - Branch Prediction Disable, on VIA C3.
BPE - Branch Prediction Enable, on VIA C3.
Multiple commands can be passed at once.
Running SetMul on a K6 mobile / VIA C3 without parameters gives the current
speed. It will also give the multiplier range and parameters that apply.
Also supported are 4 or 5 wide raw bit patterns: like '1010b' or '01010b'. But
these values are not checked for support, and allow for faulty register input!
OPERATING SYSTEM COMPATIBILITY-Compatible with MS-DOS, both with and without EMM386 loaded.
-Compatible with Windows 95, 98 and ME. -SetMul requires CWSDPMI.exe or a compatible DPMI host.
-SetMul sets up a Ring0 exploit to get privileged access to the CPU registers.
-Windows NT/2K/XP/Vista/7/8 or later cannot be fooled,
these systems are not supported.
DISCLAIMERUse SetMul at your own risk! The author takes no responsibility for loss
of data or damage to hardware through the use of this software.
This program is for vintage hardware hobby use only. It has not been
sufficiently tested to be used while simultaneously working on important data.
ALTERNATIVESC3Mul for DOS, all functionality retained in SetMul. Relies on CWSDPR0.exe.
WCPUID for Windows (works with Samuel 1, does not work with Ezra-T)
CrystalCPUID for Windows (Does not work with Samuel 1, works with Ezra-T)
K6DOS config.sys Driver for DOS, and K6Speed for windows.
AMD K6 Central Tweaking Unit '
CTU', for Windows.
http://falcosoft.hu/ has DOS-based multiplier tools for AMD Athlon etc.
NEW SINCE UPDATE v1.1 of 20-05-2014-Fixed protection fault when running SetMul on a 486 system
-K6-2+/III+ : Exclusively toggle L1 cache: parameters L1DX / L1EX
-Pentium Pro/2/3 toggle L2 cache: parameters L2D / L2E
-Winchip C6 toggle I-cache: parameters ICD / ICE
-Pentium P54C test register "TR12" options. Parameters:
BPD - Disable Branch Prediction
VPD - Disable V Pipeline
L1DX - Disable L1 cache exclusively
CCD - Disable L1 code cache
DCD - Disable L1 data cache
PFE - Pentium Features Enable; Resets the above TR12 options to default.
The status of register TR12 cannnot be read by design.
NEW SINCE UPDATE v1.2 of 08-07-2015-Cyrix 5x86 support.
It can switch between the jumpered startup multiplier and 1.0x and back.
Some intended functions do not work, despite following the datasheet by the letter.
Like Multiplier readout, and Half-speed enable/disable (Parameter HSE and HSD).
Half-speed may only come to effect in idle mode of the CPU. Regardless,
these options remain in the program for now.
-Recompiled, seems to have fixed protection fault in v1.2A
NEW SINCE UPDATE v1.21 of 22-2-2017-Shows the bootup multiplier of the Pentium Pro, II and III. (Cannot change it).
DEVELOPMENT LOG03-2014 - Initial release 1.0, based on the C3Mul source:
-Replaced the external ASM file with inline routines (get_vendor_id + get_cpuid)
-Changed text messages, more info is written to screen.
-Replaced Nehemiah+Ezra-T PowerSaver routines with longhaul-v2 from CrystalCPUID.
-New format of multiplier setting table.
-Read back of multiplier from MSR with separate Read back table.
-Added windows 98 detection. EDIT: Changed to NT detection.
-Added K6 Mobile support. Added L2 cache size detection.
-Verified to set and read back properly on: Samuel1+Samuel2+Ezra-T+Nehemiah
and K6-2+ (on all settings).
-Added Ring0 LDT Call Gate system. Now also works with default CWSDPMI and in
Windows 9X.
-Added L1 Cache Disable/Enable, for any 486+.
-Added L2 Cache Disable/Enable, for supported CPUs.
-Parameter handling now unaffected by the order in which parameters are passed.
-Text highlight through console text colors.
-Rewrote IRQ masking in Ring 0 Assembly, now assumes the existing
IRQ-0 timer setting is practical: by default it has the smallest 55ms interval.
-Now does CPUID and MHz calculation for any Pentium-class or later. CREDITSAuthor: G. Broers
http://members.quicknet.nl/lm.broers/Credits to the original C3MUL author, 2001/4/28, for Samuel and Ezra
http://blue.ribbon.to/~als4kmaniac/i2/Credits to CrystalCPUID by hiyohiyo.
For the longhaul_v2 and part of the Powersaver routines.
Credits to RayeR for the idea on Ring0 access through DJGPP.