Well, I've gotten the testbed setup now and did a quick test with an SXL-33. Report attached.

CPU-Z reported the motherboard as an ECS Elitegroup, but it is a Daewoo AL486V-D. Everything else appeared correct.

I'll report back with benchmark scores after I fine tune the BIOS settings. I should also try running it with L1 disabled to ensure CPU-Z reports L1 as disabled.

feipoa wrote on 2020-04-16, 14:03:

Does running CPU-Z in NT4 provide any additional information over running it in Win95?

No, the version is really targeted for win9x.

Thanks for the test on the SXL, please save the TXT reports rather than the HTML, the HTML do not contain the registers outputs.

Just tried it again in my Socket 5 PC. It's a success! Haven't tried to see if it still suffers from K5 crash yet, but I'll try soon.
Edited that out because it was unnecessary here. Sorry.

Test results with the SXL2-50 installed and running at 2x25=50 MHz and a Cyrix FasMath CX-83D87, running at 25 MHz.

CPU-Z is reporting the incorrect multiplier. Is CPU-Z able to read the Configuration Control Register 0 (aka, CCR0) bit 6? If it is set high (1) that means the 2x multiplier is active, if set low (0) the CPU is in 1x mode.

Here are the benchmark results.

Screenshot indicating the wrong motherboard brand.

Report file in text format.

TechieDude wrote on 2020-04-16, 21:01:

Just tried it again in my Socket 5 PC. It's a success! Haven't tried to see if it still suffers from K5 crash yet, but I'll try soon.
Edited that out because it was unnecessary here. Sorry.

Great, thanks for the feedback.

feipoa wrote on 2020-04-17, 06:42:

Test results with the SXL2-50 installed and running at 2x25=50 MHz and a Cyrix FasMath CX-83D87, running at 25 MHz.
CPU-Z is reporting the incorrect multiplier. Is CPU-Z able to read the Configuration Control Register 0 (aka, CCR0) bit 6? If it is set high (1) that means the 2x multiplier is active, if set low (0) the CPU is in 1x mode.
SXL2-50-w95_wrong_multiplier.jpg

Ah yes good point, I add this and update the binary. Thanks !
Your BIOS string is

140-0100-001131-00101111-080893-ALI1429

and according to https://www.wimsbios.com/aminumbers.jsp, 1131 is ECS. Weird.

It is possible that ECS made these motherboards for Daewoo. It is also possible that wimsbios is wrong.

I've added the 2x multiplier detection from CCR0. I wonder if the switch 1x / 2x works dynamically, do you have a tool that allows to change CCR0 ?

http://download.cpuid.com/betas/cpuz_w95.zip

Yes, I can change it in DOS. I will can switch it back to 1x and ensure that CPUID is behaving. I also want to disable L1 to ensure CPUID shows the cache as disabled.

CuPid wrote on 2020-04-16, 12:54:

appiah4 wrote on 2020-04-16, 12:38:

It's a Cyrix 6x86MX PR233 running on Windows 98SE

Ah, there are no MSR read on that system, it must be something else.
Can you please copy that cpuz.ini in the same directory as cpuz_w9x.exe, and tell me if the program starts this time ?

I tried this .ini with the below latest beta executable and it still crashes.

This particular system also crashes when loading SpeedSys and requires the /SP switch to disable PCI/ISA detection.

It might be related?

appiah4 wrote on 2020-04-17, 10:19:

I tried this .ini with the below latest beta executable and it still crashes.

This particular system also crashes when loading SpeedSys and requires the /SP switch to disable PCI/ISA detection.

It might be related?

Yes definitely, but PCI detection was disabled in the ini.
By disabling ISA I wonder if it would disable the DIRs registers reading, that would explain a lot. I have no flag in the ini to disable that, but it could be easily and quickly removed for testing purpose. I keep you posted.

CuPid wrote on 2020-04-17, 10:25:

appiah4 wrote on 2020-04-17, 10:19:

I tried this .ini with the below latest beta executable and it still crashes.

This particular system also crashes when loading SpeedSys and requires the /SP switch to disable PCI/ISA detection.

It might be related?

Yes definitely, but PCI detection was disabled in the ini.
By disabling ISA I wonder if it would disable the DIRs registers reading, that would explain a lot. I have no flag in the ini to disable that, but it could be easily and quickly removed for testing purpose. I keep you posted.

Sorry for the inconvenience but if you are willing to do something about it and come up with another binary I'm ok with trying it out..

I have verified that CPU-Z shows the correct core speed and multiplier when I change the multiplier in software for the SXL2-50. However, when I disable the L1 cache entirely, CPU-Z is still reporting it as 8 KB, 2-way set associative. I think it should be greyed out entirely, or listed as "disabled".

Is CPU-Z able to display the graphic card information for VLB cards? Everything in the Graphics tab is greyed out.

The latest CPUZ 9x had broken reporting for my 9980XE and many other systems. Reporting x12 and 30000MHz is clearly impossible and I see similar on most recent systems.

I also think IVB-E is 22nm rather than 21nm, see https://en.wikipedia.org/wiki/List_of_I ... erformance

feipoa wrote on 2020-04-17, 10:44:

I have verified that CPU-Z shows the correct core speed and multiplier when I change the multiplier in software for the SXL2-50. However, when I disable the L1 cache entirely, CPU-Z is still reporting it as 8 KB, 2-way set associative. I think it should be greyed out entirely, or listed as "disabled".

Is CD bit of CCR0 set to 1 when L1 is disabled ?

feipoa wrote on 2020-04-17, 10:44:

Is CPU-Z able to display the graphic card information for VLB cards? Everything in the Graphics tab is greyed out.

No, I don't have the smallest idea about how to detect VLB or ISA cards.

I don't know. This is my control screen:

And these are the registers I can read from CTCHIP34:

1;********** Cyrix/Texas 486SLC/DLC in CX486.CFG********************
2
3INDEXPORT=22h
4DATENPORT=23h
5
6FLUSH=INVD
7
8INDEX=C0h; Configuration Control Register 0
9
10BIT=7    ;0/1 (Suspend) /SUSP input and /SUPSA output
11BIT=6    ;    (CO)     Cache-Organisation
12                 0= 2-Way
13                 1= direct mapped
14BIT=5   ;0/1 (BARB)   Flush Cache every HOLD
15BIT=4   ;0/1 (FLUSH)  /Flush input pin (DLC:E13, SLC:30)
16BIT=3   ;0/1 (KEN)    /KEN  input pin  (DLC:B12, SLC:29)
17BIT=2   ;0/1 (A20M)   /A20M input pin  (DLC:F13, SLC:31)
18BIT=1   ;0/1 (MC1) 640K-1M non-cacheable
19        ;                               (Bug in A4/A5 Stepping!)
20BIT=0   ;0/1 (NC0) First 64KB always not cacheable
21        ;                               (Real/Virtuell)
22
23INDEX=C1h; Configuration Control Register 1
24Bit=0   ; 0/1 (RPL)  output pins /RPLSET and /RPLVAL
25
26INDEX=C4h; Non Cacheable Region Register (Default=00h);
27BIT=7654321      ; A31 - A24 of starting address Region 1
28
29INDEX=C5h; Non Cacheable Region Register (Default=0Ah);
30BIT=76543210     ; A23 - A16 of starting address Region 1
31
32INDEX=C6h; Non Cacheable Region Register (Default=06h);
33BIT 7654         ; A15 - A12 of starting address Region 1
34BIT=3210         ; Size of non-cacheable Region 1
35
36INDEX=C7h; Non Cacheable Region Register (Default=00h);
37BIT=7654321      ; A31 - A24 of starting address Region 2
38
39INDEX=C8h; Non Cacheable Region Register (Default=0Ah);
40BIT=76543210     ; A23 - A16 of starting address Region 2
41
42INDEX=C9h; Non Cacheable Region Register (Default=06h);
43BIT 7654         ; A15 - A12 of starting address Region 2
44BIT=3210         ; Size of non-cacheable Region 2
45
46INDEX=CAh; Non Cacheable Region Register (Default=00h);
47BIT=7654321      ; A31 - A24 of starting address Region 3
48
49INDEX=CBh; Non Cacheable Region Register (Default=0Ah);
50BIT=76543210     ; A23 - A16 of starting address Region 3
51
52INDEX=CCh; Non Cacheable Region Register (Default=06h);
53BIT 7654         ; A15 - A12 of starting address Region 3
54BIT=3210         ; Size of non-cacheable Region 3
55
56INDEX=CDh; Non Cacheable Region Register (Default=00h);
57BIT=7654321      ; A31 - A24 of starting address Region 4
58
59INDEX=CEh; Non Cacheable Region Register (Default=0Ah);
60BIT=76543210     ; A23 - A16 of starting address Region 4

61
62INDEX=CFh; Non Cacheable Region Register (Default=06h);
63BIT 7654         ; A15 - A12 of starting address Region 4
64BIT=3210         ; Size of non-cacheable Region 4

I have a dozen more DLC/SXL software apps, but it would take some time to go through them all to see if any can read CR0.
EDIT: Note that CCR0 != CR0

appiah4 wrote on 2020-04-17, 10:38:

Sorry for the inconvenience but if you are willing to do something about it and come up with another binary I'm ok with trying it out..

On the contrary, it is always interesting to figure out what can be wrong.
Here is a version without DIRs reading. If it works, you can eventually remove cpuz.ini (that results in setting all flags back to 1).
http://download.cpuid.com/betas/cpuz_w95_noisa.zip

feipoa wrote on 2020-04-17, 11:46:

EDIT: Note that CCR0 != CR0

Yes I just realize my mistake, CD is a bit of CR0, not CCR0.

CuPid wrote on 2020-04-17, 12:08:

appiah4 wrote on 2020-04-17, 10:38:

Sorry for the inconvenience but if you are willing to do something about it and come up with another binary I'm ok with trying it out..

On the contrary, it is always interesting to figure out what can be wrong.
Here is a version without DIRs reading. If it works, you can eventually remove cpuz.ini (that results in setting all flags back to 1).

OK I downloaded this, I will try it out tonight and let you know CuPid.

I'm afraid I must report another failure, the error persists.

appiah4 wrote on 2020-04-17, 21:46:

I'm afraid I must report another failure, the error persists.

OK. I suggest that we continue in PM.

CuPiD> Is there another revision of CPU-Z you wanted me to test on the SXL-50 for the case of L1 being disabled? If not, I'll move onto another CPU on your wish list.