I think the two cards are identical.
Just the SIIG one has stickers over the same chips.

As impressive the Holtek VLB EIDE controllers are, their ISA stuff is not like that.
In reasonable ISA frequency they are the same as everybody else.
Dont handle well ISA overclock.

Recently i checked HT6550.

pshipkov wrote on 2024-05-29, 04:18:

I think the two cards are identical.
Just the SIIG one has stickers over the same chips.

Definitely no Holtek chip on the card that I have. It’s just a sticker over unpopulated contacts.

Right. Had to look again at the oic you provided.
So that ht6535 seems to be the LPT implementation actually.

pshipkov wrote on 2024-05-30, 05:06:

Right. Had to look again at the oic you provided.
So that ht6535 seems to be the LPT implementation actually.

Ahh. I see that the card with the HT6535 chop has additional LPT headers. The second LPT chip makes sense now. Thanks for helping me out there.

So my only remaining question is: "what is that 2KB SRAM chip doing" ?

Wouldn't there need to be some sort of IDE controller on the card if it was going to use a buffer?

douglar wrote on 2024-05-30, 17:31:

So my only remaining question is: "what is that 2KB SRAM chip doing" ?

Wouldn't there need to be some sort of IDE controller on the card if it was going to use a buffer?

Likely the 2K SRAM chip is visible in the ROM window of the card, and will be used by the IDE BIOS to store the drive geometries. Possibly only a small amount (like 64 bytes) of the chip is accessible, as that's all you need for that stuff.

mkarcher wrote on 2024-05-30, 17:42:

douglar wrote on 2024-05-30, 17:31:

So my only remaining question is: "what is that 2KB SRAM chip doing" ?
Wouldn't there need to be some sort of IDE controller on the card if it was going to use a buffer?

Likely the 2K SRAM chip is visible in the ROM window of the card, and will be used by the IDE BIOS to store the drive geometries. Possibly only a small amount (like 64 bytes) of the chip is accessible, as that's all you need for that stuff.

That sort of makes sense. The only nagging through is that it would have been less expensive to steal 2KB bytes of conventional memory. Why add a chip when you don't have to?

Here's the back of the card.

The 2Kb buffer is too big for what mkarcher speculated and too small for data cache.
It probably is for instructions cache to avoid the need of ROM shadowing through mobo bios.
Some SCSI controllers from that time do the same.

ECP parallel ports include support for a FIFO buffer; could it tbe that?

afaik small fifos, like 8-16 bytes

The SRAM chip is present in both cards, where one of them has the Holtek LPT IC + header and the other does not.
So, it is unlikely the SRAM buffer is LPT related.

It is not clear from the pictures how and where the SRAM pins are connected.
Looks like on the front quite a few of them go to the EPROM.

Anyhow.